JPS6448166A - Cache memory control system for parallel computers - Google Patents

Cache memory control system for parallel computers

Info

Publication number
JPS6448166A
JPS6448166A JP62205750A JP20575087A JPS6448166A JP S6448166 A JPS6448166 A JP S6448166A JP 62205750 A JP62205750 A JP 62205750A JP 20575087 A JP20575087 A JP 20575087A JP S6448166 A JPS6448166 A JP S6448166A
Authority
JP
Japan
Prior art keywords
data
cell
cache memory
access request
overhead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62205750A
Other languages
Japanese (ja)
Other versions
JPH0750466B2 (en
Inventor
Hiroaki Ishihata
Yuko Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62205750A priority Critical patent/JPH0750466B2/en
Publication of JPS6448166A publication Critical patent/JPS6448166A/en
Publication of JPH0750466B2 publication Critical patent/JPH0750466B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce the overhead for inter-processor communication and data relaying, by transferring data to a cell of the access request source if desired data exists in the cache memory on a cell which the data access request passes. CONSTITUTION:Each cell 2-1 is provided with a cache memory 5-i in which data which at least this cell itself requires or data transferred through this cell on demand is held; and if desired data exists on a cache memory 5-k of a cell 2-k which the data access request from a certain cell passes, this data is transferred to the cell which issues the data access request. Thus, the overhead for inter-processor communication in case of data access to another cell or the overhead for data relaying is reduced.
JP62205750A 1987-08-19 1987-08-19 Parallel computer cache memory control system Expired - Lifetime JPH0750466B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205750A JPH0750466B2 (en) 1987-08-19 1987-08-19 Parallel computer cache memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205750A JPH0750466B2 (en) 1987-08-19 1987-08-19 Parallel computer cache memory control system

Publications (2)

Publication Number Publication Date
JPS6448166A true JPS6448166A (en) 1989-02-22
JPH0750466B2 JPH0750466B2 (en) 1995-05-31

Family

ID=16512036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205750A Expired - Lifetime JPH0750466B2 (en) 1987-08-19 1987-08-19 Parallel computer cache memory control system

Country Status (1)

Country Link
JP (1) JPH0750466B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287668A (en) * 1989-03-31 1990-11-27 American Teleph & Telegr Co <Att> Reconstractable signal processor
JP2007052790A (en) * 2005-08-19 2007-03-01 Internatl Business Mach Corp <Ibm> System, method, computer program and device for communicating command parameter between processor and memory flow controller
US7778271B2 (en) 2005-08-19 2010-08-17 International Business Machines Corporation Method for communicating instructions and data between a processor and external devices
US7930457B2 (en) 2005-08-19 2011-04-19 International Business Machines Corporation Channel mechanisms for communicating with a processor event facility

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287668A (en) * 1989-03-31 1990-11-27 American Teleph & Telegr Co <Att> Reconstractable signal processor
JP2007052790A (en) * 2005-08-19 2007-03-01 Internatl Business Mach Corp <Ibm> System, method, computer program and device for communicating command parameter between processor and memory flow controller
US7778271B2 (en) 2005-08-19 2010-08-17 International Business Machines Corporation Method for communicating instructions and data between a processor and external devices
US7869459B2 (en) 2005-08-19 2011-01-11 International Business Machines Corporation Communicating instructions and data between a processor and external devices
US7930457B2 (en) 2005-08-19 2011-04-19 International Business Machines Corporation Channel mechanisms for communicating with a processor event facility
US8024489B2 (en) 2005-08-19 2011-09-20 International Business Machines Corporation System for communicating command parameters between a processor and a memory flow controller

Also Published As

Publication number Publication date
JPH0750466B2 (en) 1995-05-31

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