JPS644856A - Parallel processing system - Google Patents

Parallel processing system

Info

Publication number
JPS644856A
JPS644856A JP62161626A JP16162687A JPS644856A JP S644856 A JPS644856 A JP S644856A JP 62161626 A JP62161626 A JP 62161626A JP 16162687 A JP16162687 A JP 16162687A JP S644856 A JPS644856 A JP S644856A
Authority
JP
Japan
Prior art keywords
processors
digit
different
information transfer
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62161626A
Other languages
Japanese (ja)
Other versions
JP2743994B2 (en
Inventor
Setsu Suzuoka
Shigeru Koyanagi
Junichi Fujita
Sadao Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62161626A priority Critical patent/JP2743994B2/en
Publication of JPS644856A publication Critical patent/JPS644856A/en
Application granted granted Critical
Publication of JP2743994B2 publication Critical patent/JP2743994B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To execute a high speed processing by a simple system constitution, by coupling each of (m) sets of processors whose numbers are different by one digit, when a serial number of an (m) scale-notation number beginning with '0' has been put to processors of power pieces of an integer (m) >=2. CONSTITUTION:In a system consisting of N (=ml, m is an integer >=2) sets of processors, when N-1 is brought to an (m) scale-notation display, its digit number is l (=logmN), therefore, when (m) sets of processors whose numbers are different by one digit in the serial number extending from '0' to N-1 are coupled by a coupling means, the number of information transfer lines coupled to each processor becomes l. Also, between the processors whose numbers are different by one digit, an information transfer of one step can be transferred through the coupling means, therefore, even between the processors in which all of l digits are different and which are separated farthest, as for the number of steps required for an information transfer, l is enough. Accordingly, the more (m) is increased, the less the number of information transfer lines connected to each information processor can be curtailed, and the hardware quantity can also be curtailed. Also, the transfer time can be decreased.
JP62161626A 1987-06-29 1987-06-29 Parallel processing system Expired - Fee Related JP2743994B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62161626A JP2743994B2 (en) 1987-06-29 1987-06-29 Parallel processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161626A JP2743994B2 (en) 1987-06-29 1987-06-29 Parallel processing system

Publications (2)

Publication Number Publication Date
JPS644856A true JPS644856A (en) 1989-01-10
JP2743994B2 JP2743994B2 (en) 1998-04-28

Family

ID=15738759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161626A Expired - Fee Related JP2743994B2 (en) 1987-06-29 1987-06-29 Parallel processing system

Country Status (1)

Country Link
JP (1) JP2743994B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02183860A (en) * 1989-01-11 1990-07-18 Agency Of Ind Science & Technol Data transmission system
WO2007099950A1 (en) * 2006-03-03 2007-09-07 Nec Corporation Processor array system having function for data reallocation between high-speed pe
JP2008097528A (en) * 2006-10-16 2008-04-24 Fujitsu Ltd Computer cluster

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5093753A (en) * 1973-12-21 1975-07-26
JPS60140457A (en) * 1983-12-28 1985-07-25 Hitachi Ltd computer system
JPS60175174A (en) * 1984-02-21 1985-09-09 Agency Of Ind Science & Technol Parallel data transfer system
JPS60181962A (en) * 1984-02-29 1985-09-17 Fujitsu Ltd Communicating system in parallel computer
JPS60196042A (en) * 1984-03-19 1985-10-04 Nec Eng Ltd Loop bus control system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5093753A (en) * 1973-12-21 1975-07-26
JPS60140457A (en) * 1983-12-28 1985-07-25 Hitachi Ltd computer system
JPS60175174A (en) * 1984-02-21 1985-09-09 Agency Of Ind Science & Technol Parallel data transfer system
JPS60181962A (en) * 1984-02-29 1985-09-17 Fujitsu Ltd Communicating system in parallel computer
JPS60196042A (en) * 1984-03-19 1985-10-04 Nec Eng Ltd Loop bus control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02183860A (en) * 1989-01-11 1990-07-18 Agency Of Ind Science & Technol Data transmission system
WO2007099950A1 (en) * 2006-03-03 2007-09-07 Nec Corporation Processor array system having function for data reallocation between high-speed pe
US7783861B2 (en) 2006-03-03 2010-08-24 Nec Corporation Data reallocation among PEs connected in both directions to respective PEs in adjacent blocks by selecting from inter-block and intra block transfers
JP2008097528A (en) * 2006-10-16 2008-04-24 Fujitsu Ltd Computer cluster

Also Published As

Publication number Publication date
JP2743994B2 (en) 1998-04-28

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees