JPS6448923U - - Google Patents
Info
- Publication number
- JPS6448923U JPS6448923U JP14329687U JP14329687U JPS6448923U JP S6448923 U JPS6448923 U JP S6448923U JP 14329687 U JP14329687 U JP 14329687U JP 14329687 U JP14329687 U JP 14329687U JP S6448923 U JPS6448923 U JP S6448923U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input terminal
- gate
- operational amplifier
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案になるＡＧＣ回路の一実施例を
示す回路図、第２図は従来のＡＧＣ回路を示す回
路図である。
１……入力端子、２……演算増幅器（オペアン
プ）、３……反転入力端子、４……非反転入力端
子、５……電界効果トランジスタ（ＦＥＴ）、６
……出力端子、Ｃ１……コンデンサ、Ｄ１……ダ
イオード、Ｒ１〜Ｒ６……抵抗。
FIG. 1 is a circuit diagram showing an embodiment of the AGC circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional AGC circuit. 1... Input terminal, 2... Operational amplifier (op-amp), 3... Inverting input terminal, 4... Non-inverting input terminal, 5... Field effect transistor (FET), 6
...output terminal, C1 ...capacitor, D1 ...diode, R1 to R6 ...resistance.
Claims (1)
接続され、非反転入力端子が接地された演算増幅
器と、この演算増幅器の出力側と反転入力端子と
の間に接続された第２の抵抗と、ゲート以外の一
方の端子が前記演算増幅器の反転入力端子に接続
され、他方の端子が第３の抵抗を介して前記演算
増幅器の出力側に接続された電界効果トランジス
タと、前記第３の抵抗に並列に接続され、抵抗値
が前記第３の抵抗の抵抗値よりも小さい第４の抵
抗と、前記電界効果トランジスタのゲートに接続
された第５の抵抗と、一端がこの第５の抵抗と前
記電界効果トランジスタのゲートとの接続点に接
続され、他端がダイオードを介して出力端子に接
続され、前記第５の抵抗と共に前記電界効果トラ
ンジスタのゲートに供給される電圧の分圧抵抗を
成す第６の抵抗と、この第６の抵抗及び前記第５
の抵抗に並列に接続されたコンデンサとより構成
したことを特徴とする自動利得制御回路。 an operational amplifier whose input terminal is connected to the inverting input terminal via a first resistor and whose non-inverting input terminal is grounded; and a second resistor connected between the output side of the operational amplifier and the inverting input terminal. and a field effect transistor having one terminal other than the gate connected to the inverting input terminal of the operational amplifier and the other terminal connected to the output side of the operational amplifier via a third resistor; a fourth resistor connected in parallel with the resistor and having a resistance value smaller than the resistance value of the third resistor; a fifth resistor connected to the gate of the field effect transistor; and one end of the fifth resistor. and the gate of the field effect transistor, the other end is connected to the output terminal via a diode, and a voltage dividing resistor for the voltage supplied to the gate of the field effect transistor together with the fifth resistor. a sixth resistor, and a sixth resistor and the fifth resistor.
An automatic gain control circuit characterized by comprising a capacitor connected in parallel to a resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14329687U JPS6448923U (en) | 1987-09-19 | 1987-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14329687U JPS6448923U (en) | 1987-09-19 | 1987-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6448923U true JPS6448923U (en) | 1989-03-27 |
Family
ID=31409990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14329687U Pending JPS6448923U (en) | 1987-09-19 | 1987-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6448923U (en) |
-
1987
- 1987-09-19 JP JP14329687U patent/JPS6448923U/ja active Pending
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