JPS6449253A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6449253A
JPS6449253A JP62205969A JP20596987A JPS6449253A JP S6449253 A JPS6449253 A JP S6449253A JP 62205969 A JP62205969 A JP 62205969A JP 20596987 A JP20596987 A JP 20596987A JP S6449253 A JPS6449253 A JP S6449253A
Authority
JP
Japan
Prior art keywords
output
external
module
during
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205969A
Other languages
Japanese (ja)
Inventor
Hideki Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62205969A priority Critical patent/JPS6449253A/en
Publication of JPS6449253A publication Critical patent/JPS6449253A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of external terminals and to execute a high- speed test operation by a method wherein an external terminal for external output use during an operation is bonded with an output for external use only during a test operation of another module. CONSTITUTION:During an ordinary operation, a control signal at an L level is impressed on an external control terminal S; an output A1 of an AND gate 11 becomes always at the L level irrespective of an output A of a module 1. An output B of a module 2 is output to an output D of an EXOR gate 12 and is transmitted to an external terminal M2. During a test operation, a signal C at an H level is impressed on the terminal S; accordingly, the output A of the module 1 is output at the output A1. The output D as an exclusive OR value of the output A and the output of the module 2 is output to the external terminal M2. Accordingly, if a waveform of the output D is compared with a previously established waveform, an integrated circuit can be tested.
JP62205969A 1987-08-19 1987-08-19 Semiconductor integrated circuit Pending JPS6449253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205969A JPS6449253A (en) 1987-08-19 1987-08-19 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205969A JPS6449253A (en) 1987-08-19 1987-08-19 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6449253A true JPS6449253A (en) 1989-02-23

Family

ID=16515713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205969A Pending JPS6449253A (en) 1987-08-19 1987-08-19 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6449253A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736722A (en) * 1993-07-15 1995-02-07 Nec Corp Hierarchical test pattern generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736722A (en) * 1993-07-15 1995-02-07 Nec Corp Hierarchical test pattern generator

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