JPS6449337A - Parallel synchronizing circuit - Google Patents

Abstract

PURPOSE:To miniaturize a circuit scale with obtaining one comparator by dividing a high order group digital signal into an (m) number of parallel bits, preparing an first or an (m)-th signal string which is (m)-divided and outputting them in separate systems. CONSTITUTION:With synchronizing with a timing signal (f/3) of a Q output of an FF14 to three-divide a reference clock signal CLK(f), a first signal string (f) is outputted from an output system FF11 of a signal dividing circuit 10, a second signal string (h) is outputted from an FF12 and a third signal string (j) is outputted from an FF13. Thus, each time a first dividing frame pattern signal is stored to shift registers 20a, 30a and 40a in frame pattern detecting circuits 20, 30 and 40, a detecting signal is outputted from AND circuits 23, 33 and 45. The input timing of a signal from AND circuits 81-83 and the input timing of a pulse signal from a pulse generating circuit 84 are compared by a COMP85 and when the timings are not coincident, an AND circuit 86 is closed only for one clock [CLK(f/3)].