JPS6449896U - - Google Patents
Info
- Publication number
- JPS6449896U JPS6449896U JP14214487U JP14214487U JPS6449896U JP S6449896 U JPS6449896 U JP S6449896U JP 14214487 U JP14214487 U JP 14214487U JP 14214487 U JP14214487 U JP 14214487U JP S6449896 U JPS6449896 U JP S6449896U
- Authority
- JP
- Japan
- Prior art keywords
- segment
- grid
- display
- circuit
- luminance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図は本考案に係る表示器駆動回路のブロツ
ク図、第２図は該回路に装備される表示器の各セ
グメントの形状を表わす図表、第３図は該回路の
動作を表わすタイミングチヤート、第４図は表示
器の表示パターンの一例を示す図、第５図は従来
回路のブロツク図、第６図は従来回路に装備され
る表示器の各セグメント形状を表わす図表、第７
図は従来回路の動作を表わすタイミングチヤート
である。
１……表示器、４……セグメントドライバー、
７……グリツドドライバー、８……低輝度セグメ
ント検出回路、１１……制御回路。
FIG. 1 is a block diagram of a display drive circuit according to the present invention, FIG. 2 is a diagram showing the shape of each segment of the display device installed in the circuit, and FIG. 3 is a timing chart showing the operation of the circuit. FIG. 4 is a diagram showing an example of the display pattern of the display device, FIG. 5 is a block diagram of a conventional circuit, FIG. 6 is a diagram showing the shape of each segment of the display device installed in the conventional circuit, and FIG.
The figure is a timing chart showing the operation of a conventional circuit. 1...Display unit, 4...Segment driver,
7...Grid driver, 8...Low brightness segment detection circuit, 11...Control circuit.
Claims (1)
種々の表示パターンを形成すべき複数の表示ブロ
ツクの夫々にグリツド電極が配設された表示器１
と、該表示器１の各グリツド電極及び各セグメン
ト電極へ夫々駆動パルスを供給するセグメントド
ライバー４及びグリツドドライバー７と、表示パ
ターンに応じたデータを発生するデータ発生回路
２と、前記両ドライバー４，７とデータ発生回路
２との間に介装した制御回路とから構成され、低
輝度セグメントには高輝度セグメントに対するよ
り大なるデユーテイの駆動パルスを印加すること
により輝度補正が施されるダイナミツク駆動方式
の表示器駆動回路に於いて、前記制御回路１１は
、各グリツド電極に対する駆動パルスの発生期間
にデータ発生回路２からのデータに基づいて点灯
セグメントを指定する為のセグメント制御信号Ａ
を作成する第１制御部と、点灯セグメントに低輝
度セグメントが含まれているか否かを表示ブロツ
ク毎に検出する回路８と、表示器１の全点灯セグ
メントに対する駆動パルス発生周期Ｔの前半或は
後半の何れか一方の期間にて各グリツドに対し小
なるデユーテイの駆動パルスＰｇ１を順次発生す
る為の第１のグリツド制御信号Ｂを作成する第２
制御部と、前記周期Ｔの他方の期間にて前記検出
回路８の出力に基づき低輝度セグメントが含まれ
る表示ブロツクのグリツド電極に対し大なるデユ
ーテイの駆動パルスＰｇ２を発生する為の第２の
グリツド制御信号Ｃを作成する第３制御部とから
構成され、前記セグメント制御信号Ａ及び両グリ
ツド制御信号Ｂ，Ｃは夫々セグメントドライバー
４及びグリツドドライバー７へ接続され、前記駆
動パルス発生周期Ｔを通じて、低輝度セグメント
には高輝度セグメントに対するより大なるデユー
テイのグリツド駆動パルスＰｇとセグメント駆動
パルスＰｓが供給されることを特徴とする表示器
駆動回路。 A display device 1 in which a grid electrode is arranged in each of a plurality of display blocks in which low-luminance and high-luminance segments are mixed and various display patterns are to be formed.
, a segment driver 4 and a grid driver 7 that supply drive pulses to each grid electrode and each segment electrode of the display 1, a data generation circuit 2 that generates data according to a display pattern, and both drivers 4. , 7 and a control circuit interposed between the data generation circuit 2, and a dynamic drive in which brightness correction is applied to the low brightness segment by applying a drive pulse with a higher duty than the high brightness segment. In the display drive circuit of this type, the control circuit 11 generates a segment control signal A for specifying lighting segments based on data from the data generation circuit 2 during the generation period of drive pulses for each grid electrode.
a circuit 8 that detects for each display block whether a low-luminance segment is included in the lighting segments; A second grid control signal B for generating a first grid control signal B for sequentially generating drive pulses Pg1 with a small duty for each grid during one of the latter half periods.
and a second drive pulse Pg2 for generating a large duty driving pulse Pg2 to the grid electrode of the display block including the low luminance segment based on the output of the detection circuit 8 during the other period of the period T. The segment control signal A and both grid control signals B and C are connected to the segment driver 4 and the grid driver 7, respectively, and are controlled throughout the drive pulse generation period T. . A display driving circuit characterized in that the low-luminance segment is supplied with a grid driving pulse Pg and a segment driving pulse Ps having a duty greater than that of the high-luminance segment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987142144U JPH0741032Y2 (en) | 1987-09-17 | 1987-09-17 | Display drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987142144U JPH0741032Y2 (en) | 1987-09-17 | 1987-09-17 | Display drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6449896U true JPS6449896U (en) | 1989-03-28 |
| JPH0741032Y2 JPH0741032Y2 (en) | 1995-09-20 |
Family
ID=31407843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987142144U Expired - Lifetime JPH0741032Y2 (en) | 1987-09-17 | 1987-09-17 | Display drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0741032Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60189794A (en) * | 1984-03-09 | 1985-09-27 | シャープ株式会社 | Driving system for display element |
-
1987
- 1987-09-17 JP JP1987142144U patent/JPH0741032Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60189794A (en) * | 1984-03-09 | 1985-09-27 | シャープ株式会社 | Driving system for display element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0741032Y2 (en) | 1995-09-20 |
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