JPS6450141A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6450141A
JPS6450141A JP62206173A JP20617387A JPS6450141A JP S6450141 A JPS6450141 A JP S6450141A JP 62206173 A JP62206173 A JP 62206173A JP 20617387 A JP20617387 A JP 20617387A JP S6450141 A JPS6450141 A JP S6450141A
Authority
JP
Japan
Prior art keywords
data
store
executed
storage means
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62206173A
Other languages
Japanese (ja)
Inventor
Yasuaki Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62206173A priority Critical patent/JPS6450141A/en
Publication of JPS6450141A publication Critical patent/JPS6450141A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To surely and simply execute the load/store instruction test of a buffer storage means, by allowing the titled processor to have store operation control information by which a store operation can be executed only to one of the buffer storage means or a main storage means. CONSTITUTION:From a data processing means 1, a store instruction to a buffer storage means 3 and a main storage means 2 is executed. Subsequently, from the means 1, a loading request of a data A is executed, and since a data does not exist, the means 3 reads out the data A from the means 2 and registers it to the means 3. From the means 1, a store instruction for rewriting the data A to B is issued. As for the means 3, store inhibiting information is given, therefore, only in the means 2, the data A is rewritten to B. Subsequently, from the means 1, the loading instruction is issued again. In this case, in the means 3, the data A is to exist, whether the data which has been read out is A or not is decided by the means 1, and a load instruction test of the means 3 for deciding to be normal, and an incorrect operation, in case of the data A, and others, respectively can be executed.
JP62206173A 1987-08-19 1987-08-19 Information processor Pending JPS6450141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62206173A JPS6450141A (en) 1987-08-19 1987-08-19 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62206173A JPS6450141A (en) 1987-08-19 1987-08-19 Information processor

Publications (1)

Publication Number Publication Date
JPS6450141A true JPS6450141A (en) 1989-02-27

Family

ID=16519017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62206173A Pending JPS6450141A (en) 1987-08-19 1987-08-19 Information processor

Country Status (1)

Country Link
JP (1) JPS6450141A (en)

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