JPS6450614A - Digital signal processing circuit - Google Patents

Digital signal processing circuit

Info

Publication number
JPS6450614A
JPS6450614A JP20770887A JP20770887A JPS6450614A JP S6450614 A JPS6450614 A JP S6450614A JP 20770887 A JP20770887 A JP 20770887A JP 20770887 A JP20770887 A JP 20770887A JP S6450614 A JPS6450614 A JP S6450614A
Authority
JP
Japan
Prior art keywords
circuit
sample string
attenuators
multiplying
attenuator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20770887A
Other languages
Japanese (ja)
Inventor
Koji Fukuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP20770887A priority Critical patent/JPS6450614A/en
Publication of JPS6450614A publication Critical patent/JPS6450614A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To change smoothly the characteristic while evading an abnormal frequency characteristic or phase characteristic by devising the titled circuit such that an input sample string is outputted directly not through a multiplying cirucit till the changeover of a multiplication coefficient of the multiplier circuit is finished when a multiplication factor of the multiplying circuit is changed over. CONSTITUTION:A digital signal processing circuit is provided with, e.g., the same multiplying circuits 22-30, and the circuit 22 has multiplying circuit sections 221, 222 having, e.g., two multiplication factors to be switched in its inside. Moreover, 1st and 2nd attenuators 32, 34 are provided to an input sample string x(n). A 3rd attenuator 36 outputs an output sample string y(n)' from an output sample string y(n) of an adder circuit 12. The 2nd adder 38 uses the 1st and 3rd attenuators 32, 36 to output an output sample string z(n). Then the attenuation is infinite in the 1st attenuator 32 before the changeover of a multiplication coefficient and is zero in the 2nd and 3rd attenuators 34, 36 as a 1st state. Moreover, the attenuation is infinite in the 2nd and 3rd attenuators 34, 36 and zero in the 1st attenuator as a 2nd state.
JP20770887A 1987-08-20 1987-08-20 Digital signal processing circuit Pending JPS6450614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20770887A JPS6450614A (en) 1987-08-20 1987-08-20 Digital signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20770887A JPS6450614A (en) 1987-08-20 1987-08-20 Digital signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6450614A true JPS6450614A (en) 1989-02-27

Family

ID=16544248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20770887A Pending JPS6450614A (en) 1987-08-20 1987-08-20 Digital signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6450614A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04140827A (en) * 1990-10-02 1992-05-14 Fujitsu Ten Ltd Arithmetic method for floating point display data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04140827A (en) * 1990-10-02 1992-05-14 Fujitsu Ten Ltd Arithmetic method for floating point display data

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