JPS6453250A - Bus controller - Google Patents

Abstract

PURPOSE:To ensure the effective use of a common bus by sending data on a buffer memory to a processor without starting the common bus in such a case where the buffer memory stores the data on the shared memory to which the processor is going to access and at the same time said data is valid. CONSTITUTION:A bus controller 102 contains a data buffer 201 which stores temporarily the data in a shared memory 105 and at the same time an address signal line 123 of a common bus 112 is connected to an address discriminating circuit 202. Then it is decided by referring to a data buffer table 204 whether the buffer 201 contains or not the data on access to be given to the bus 112 from a processor 101 and the address of the memory 105 to be accessed and whether said data are updated by another processor or not. In case said data are contained in the buffer 201 and not updated by another processor 103 neither, these data are transferred to the processor 101 without starting the bus 112. Thus the starting frequency of the bus 112 can be reduced for both bus controllers 102 and 104. Then the availability of the bus 112 is improved.