JPS6453560A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6453560A
JPS6453560A JP21068187A JP21068187A JPS6453560A JP S6453560 A JPS6453560 A JP S6453560A JP 21068187 A JP21068187 A JP 21068187A JP 21068187 A JP21068187 A JP 21068187A JP S6453560 A JPS6453560 A JP S6453560A
Authority
JP
Japan
Prior art keywords
oxide film
field oxide
silicide layer
platinum silicide
dicing line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21068187A
Other languages
Japanese (ja)
Inventor
Tetsuo Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21068187A priority Critical patent/JPS6453560A/en
Publication of JPS6453560A publication Critical patent/JPS6453560A/en
Pending legal-status Critical Current

Links

Landscapes

  • Formation Of Insulating Films (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To prevent cracks which are generated during a dicing process from affecting a chip product, by leaving an oxide film on a dicing line to be etched with plasma, and forming a platinum silicide layer between the chip product and the oxide film on the dicing line. CONSTITUTION:A semiconductor device comprises a silicon substrate or epitaxial layer 1, a field oxide film 3, a platinum silicide layer 3, and a nitride film 4 for passivation. Now, though the field oxide film 2 which is formed on the silicon substrate or epitaxial layer 1 is etched during contact holes being formed, only the part of the field oxide film 2 between the field oxide film 2 on the dicing line and each the adjacent chip product is etched, with the part of the field oxide film 2 on the dicing line being still left. The platinum silicide layer 3 then coats the contact section, and the nitride film 4 for passivation is thereafter deposited over the substrate body. Moreover, when the field oxide film is formed on the both sides of the platinum silicide layer 3 to provide an oxide film isolated structure, the field oxide films absorb all of cracks which are generated during dicing process; therefore, the cracks are effectively prevented from affecting the chip products.
JP21068187A 1987-08-25 1987-08-25 Semiconductor device Pending JPS6453560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21068187A JPS6453560A (en) 1987-08-25 1987-08-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21068187A JPS6453560A (en) 1987-08-25 1987-08-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6453560A true JPS6453560A (en) 1989-03-01

Family

ID=16593348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21068187A Pending JPS6453560A (en) 1987-08-25 1987-08-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6453560A (en)

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