JPS6454154U - - Google Patents
Info
- Publication number
- JPS6454154U JPS6454154U JP14856387U JP14856387U JPS6454154U JP S6454154 U JPS6454154 U JP S6454154U JP 14856387 U JP14856387 U JP 14856387U JP 14856387 U JP14856387 U JP 14856387U JP S6454154 U JPS6454154 U JP S6454154U
- Authority
- JP
- Japan
- Prior art keywords
- timer
- signal
- processing unit
- central processing
- download
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案に係るウオツチドツグタイマ回
路の一実施例を示すブロツク図、第２図は従来の
ウオツチドツグタイマ回路の構成例を示すブロツ
ク図である。
１…ウオツチドツグタイマ、２…ＮＡＮＤゲー
ト、３…フリツプフロツプ、４…インバータ、５
…カウンタ、Ｓ１…クロツク信号、Ｓ２，Ｓ６…
オーバフロー信号、Ｓ３…クリア信号、Ｓ４…リ
セツト信号、Ｓ５…イネーブル信号。
FIG. 1 is a block diagram showing an embodiment of a watchdog timer circuit according to the present invention, and FIG. 2 is a block diagram showing an example of the configuration of a conventional watchdog timer circuit. 1... Watchdog timer, 2... NAND gate, 3... Flip-flop, 4... Inverter, 5
...Counter, S1 ...Clock signal, S2 , S6 ...
Overflow signal, S3 ...clear signal, S4 ...reset signal, S5 ...enable signal.
Claims (1)
常を通知する第１のタイマと、 前記中央処理装置によるダウンロードの開始と
同時に計時を開始し、該ダウンロードに要する通
常の時間より長い予め設定された時間の経過に伴
なつて信号を発生する第２のタイマと、 前記中央処理装置によるダウンロードの開始と
同時に前記第１のタイマをリセツトするとともに
、当該ダウンロードの終了を示す信号もしくは前
記第２のタイマの出力信号のうち発生タイミング
の早い方の信号により前記第１のタイマのリセツ
トを解除する手段と を具備したことを特徴とするウオツチドツグタイ
マ回路。[Claims for Utility Model Registration] A first timer that notifies the central processing unit of an abnormality if a clear signal is not input, and a timer that starts timing at the same time as the central processing unit starts downloading, and the normal time required for the download. a second timer that generates a signal as a longer preset time elapses; and a signal that resets the first timer at the same time the central processing unit starts downloading and indicates the end of the download. Alternatively, a watchdog timer circuit comprising means for canceling the reset of the first timer by a signal having an earlier generation timing among the output signals of the second timer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14856387U JPS6454154U (en) | 1987-09-29 | 1987-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14856387U JPS6454154U (en) | 1987-09-29 | 1987-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6454154U true JPS6454154U (en) | 1989-04-04 |
Family
ID=31419994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14856387U Pending JPS6454154U (en) | 1987-09-29 | 1987-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6454154U (en) |
-
1987
- 1987-09-29 JP JP14856387U patent/JPS6454154U/ja active Pending
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