JPS645511B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a device for optically recording video signals on a disk, and more particularly to a disk that is convenient for recording video signals intermittently on a single disk. It relates to a recording device.

BACKGROUND OF THE INVENTION When a video signal is optically recorded on an unrecorded disk, a modulated light beam is projected onto a rotating disk and scanned in the form of concentric or spiral tracks. By the way, in the case of an NTSC composite video signal, each field includes a vertical synchronization signal, so if one rotation of the disk corresponds to one frame, a vertical synchronization signal will be recorded every half revolution. Become. If we were to record a composite video signal continuously from the beginning to the end of a disk track, the vertical synchronization signal recording area would be aligned relatively accurately, but recording would be stopped midway through the track and then recorded again. When recording started, it was difficult to align the recording area of the vertical synchronizing signal with the recording area of the vertical synchronizing signal in the previous recording. For this reason, when the recording disc was reproduced, synchronization errors occurred at the joints between recordings, resulting in disturbances in the reproduced images. In order to solve the above-mentioned drawbacks, the inventor of the present application has filed Japanese Patent Application No. 56-49005 (Japanese Patent Application Laid-open No. 57-162890) and Japanese Patent Application No. 56-71426 (Japanese Patent Application Laid-open No. 57-189347).
proposed a recording method that can align the synchronization signals of recording signals.

By the way, in the above-mentioned new recording method, it is desirable to control the disk motor in synchronization with a vertical or frame synchronization signal when recording starts, and to control the disk motor in synchronization with a horizontal synchronization signal during recording. For this purpose, it is necessary to install a device on the disk or turntable, etc., to detect a fixed position on the circumference of the disk, and to synchronize the fixed position on the disk with a frame synchronization signal, as well as the rotational speed of the disk motor. It is required to synchronize the detected frequency signal to the horizontal synchronization signal. If the recording apparatus is configured to satisfy the above requirements, the vertical blanking period can be aligned to the same angular position on the disk even if recording is performed intermittently. However, it is difficult to synchronize the disk position detection signal and the rotational speed detection frequency signal, and there is a risk that a phase shift of less than 1H (horizontal scanning period) may occur between the previous recording and the subsequent recording. It was hot.

OBJECTS OF THE INVENTION Therefore, it is an object of the present invention to provide a disk recording device that can accurately match the synchronization signal of the previous recording and the synchronization signal of the subsequent recording to the same rotational angular position of the disk.

Structure of the Invention To achieve the above object, the present invention includes a disk drive motor for rotating a recording medium disk, a recording head for recording a composite video signal on the disk, and a drive motor for rotating the disk and the recording head. a radial feed device for causing relative feed of the disk in the radial direction; and a fixed position in the circumferential direction of the disk during rotational driving is detected from the disk or a part rotating together with the disk. a rotational position detection device; a vertical or frame synchronization reference signal circuit for generating a vertical or frame synchronization reference signal synchronized with a vertical synchronization signal or a frame synchronization signal of the composite video signal; and a position detection signal obtained from the rotational position detection device. a vertical or frame synchronization phase comparator circuit that generates a voltage corresponding to the phase difference between the vertical or frame synchronization reference signal; and a motor rotation speed detector that generates a speed detection frequency signal that corresponds to the rotation of the motor. a corrected speed detection frequency signal forming circuit that forms a corrected speed detection frequency signal corrected to synchronize the speed detection frequency signal obtained from the motor rotational speed detector with the position detection signal obtained from the rotational position detection device; , a horizontal synchronization reference signal circuit that generates a horizontal synchronization reference signal synchronized with the horizontal synchronization signal of the composite video signal; and a horizontal synchronization reference signal circuit that generates a voltage corresponding to the phase difference between the corrected speed detection frequency signal and the horizontal synchronization reference signal. a synchronization phase comparison circuit, a switch circuit that selects the output of the vertical or frame synchronization phase comparison circuit at the beginning of recording, and then selects the output of the horizontal synchronization phase comparison circuit; a motor drive circuit that drives the motor so as to zero the phase difference between the position detection signal and the vertical or frame synchronization reference signal or the phase difference between the corrected speed detection frequency signal and the horizontal synchronization reference signal based on the This invention relates to a video disc recording device equipped with the following.

Effects of the Invention According to the above invention, a corrected speed detection frequency signal forming circuit is provided, whereby the speed detection frequency signal is corrected so as to be synchronized with the position detection signal.
It becomes possible to accurately align the synchronization signal recorded earlier and the synchronization signal recorded later at a predetermined angular position on the disk.

Embodiment Next, a video disc recording apparatus according to an embodiment of the present invention will be described with reference to the drawings.

In the optical recording apparatus shown in FIG. 1, a turntable 2 and a DC motor 3 are provided as a rotation drive device for rotating a recording medium disk 1. Further, an optical recording head 4 shown surrounded by a dotted line includes a laser light source 5, a light modulator 6, and a condenser lens 7. The NTSC video signal supplied from the video signal supply circuit 8 is converted into a frequency modulated wave by the frequency modulation circuit 9 and supplied to the optical modulator 6 . Therefore, a modulated light beam is projected onto the disk 1 from the head 4, and recording corresponding to the modulated light beam is generated. Since the head 4 is connected to the radial feed device 10, the head 4 is fed in the radial direction as recording progresses, creating a spiral track TR on the disk 1 as shown in FIG.
Although not shown, tracking is controlled by a rotating mirror placed in the light beam path. In this embodiment, a spiral track is formed by feeding the head 4, but a concentric track may also be formed, or by feeding the disk 1 in its radial direction without feeding the head 4. They may also form spiral or concentric tracks.

In order to drive and control the disk 1 and motor 3 at a constant speed, a transistor 11 is connected in series with the motor 3 as a control element for voltage adjustment. Further, a motor drive circuit 12 is coupled to the base of this transistor 11 in order to supply a servo control signal to this motor control transistor 11 .
The drive circuit 12 compares a reference voltage source 13 that provides a reference voltage corresponding to a constant rotation speed with a control voltage obtained on an input line 14, and generates an output corresponding to the difference. dynamic amplifier 15
and an amplifier 16 that generates a servo control signal corresponding to the difference between the reference voltage and the control voltage.
supply to the base of

A speed detection circuit 17 for detecting the rotational speed of the disk 1 and the motor 3 connects a speed detector 18 coupled to the motor 3 and converts a speed detection frequency signal corresponding to the speed obtained from the speed detector 18 into a DC voltage. It consists of a frequency-to-voltage converter 19 for converting the frequency to the voltage, and an amplifier 20, and generates a DC control voltage corresponding to the rotation speed. A first selection switch circuit 21 is connected between the speed detection circuit 17 and the comparison amplifier circuit 12.
is provided, the speed detection voltage is supplied to the drive circuit 12 only while the switch circuit 21 is on. The speed detector 18 detects 1H (horizontal scanning period) when the motor 3 is controlled at a constant rotation speed.
It is designed to generate a pulse train with a period of 63.5μs.

22 is a stabilized voltage supply circuit, which includes a DC power supply E, a stabilization control transistor Q ₁ , voltage detection and division resistors R ₁ and R ₂ , a comparison and amplification transistor Q ₂ ,
It includes a reference Zener diode ZD and a resistor _R3 for passing a base current, and supplies a fixed voltage substantially equal to the output voltage obtained from the speed detection circuit 17 when the motor 3 is rotating at a constant rotational speed. Note that this stabilizing voltage supply circuit 22 and drive circuit 1
Since the second selection switch circuit 23 is connected between the switch circuit 2 and the switch circuit 2, the stabilized voltage is supplied only while the switch circuit 23 is on. More specifically, since the first switch circuit 21 and the second switch circuit 23 are configured to operate in opposite directions, the second switch circuit 21 operates while the first switch circuit 21 is off.
switch circuit 23 is turned on to provide a stabilized or fixed voltage.

By the way, if the motor 3 is simply driven at a constant speed, only the control based on the output of the speed detection circuit 17 is sufficient. However, if the position and rotational unevenness of the disk 1 during one rotation are to be controlled in consideration, phase control must be performed. For this reason, a rotational position detection device 24 and a horizontal synchronization control system are provided. The rotational position detection device 24 includes a light emitting element 25, a light receiving element 26, and an amplifier 27, and detects passage of a reflective surface 28 provided at a fixed position on the back surface of the disk 1. In this embodiment, the disc 1 is provided with a reflective surface 28 as a detected portion, but the turntable 2
Alternatively, it may be provided at a constant circumferential position of the motor 3. Alternatively, the rotational position may be detected magnetically or electrically instead of optically.

A frame synchronization reference signal circuit 29 that generates a reference signal for comparison with the rotational position detection signal generates one frame based on the vertical synchronization signal separated by the synchronization signal separation circuit 30 from the composite video signal obtained from the video signal supply circuit 8. This generates one pulse. That is, one pulse is generated corresponding to one rotation of the disk 1.

31 is a frame synchronization phase comparison circuit, which includes a frame synchronization reference signal circuit 29 and a rotational position detection device 2.
A phase comparator 32 connected to 4 and an amplifier 34
It compares the phases of the reference signal and the rotational position detection signal, generates a voltage corresponding to the phase difference, and supplies this to the drive circuit 12. Note that there is a first
Since a phase control output selection switch 35 is provided, the frame synchronization phase comparison output is used for control only at the selected time.

Reference numeral 36 denotes a horizontal synchronization reference signal circuit, which generates pulses at a period corresponding to the period of the horizontal synchronization signal separated by the synchronization signal separation circuit 30. Reference numeral 37 is a horizontal synchronization phase comparison circuit, in which the horizontal synchronization reference signal provided from the reference signal circuit 36 and the speed detection frequency signal obtained from the speed detector 18 at approximately 1H intervals are corrected by a correction speed detection frequency signal circuit 39. A phase comparator 38 that performs phase comparison with the signal, and an amplifier 40
It consists of The output of the horizontal synchronization phase comparison circuit 37 is coupled to the drive circuit 12 through a second phase control output selection switch 41. In this embodiment, the second phase control output selection switch 41 is configured to operate in the opposite direction to the switch 35, and is turned on after a synchronous drive state is obtained with the output of the frame synchronous phase comparison circuit 31. , forming a horizontal synchronous phase control circuit.

The corrected speed detection frequency signal forming circuit 39 is a circuit that corrects the speed detection frequency signal output from the speed detector 18 so as to synchronize it with the position detection signal obtained from the rotational position detection device 24. Therefore, this signal forming circuit 39 includes the position detecting device 24.
The output line of the synchronization detection system drive circuit 44 is connected via the delay circuit 33.

Reference numeral 43 denotes a synchronization detection circuit, which detects synchronization between the frame synchronization reference signal and the rotational position detection signal. The output of this synchronization detection circuit 43 is transmitted to the first and second switch circuits 2 via a drive circuit 44.
1 and 23 control terminals. Further, a delay circuit 45 is provided at the output stage of the drive circuit 44, and this output line 42 connects a pair of selection switches 35, 4.
1 control terminal. Furthermore, the delay circuit 45
The delay time is set longer than the delay time of the delay circuit 33. Output line 46 of delay circuit 45
is coupled to the recording start control device 47, so
When the frame synchronization reference signal and the rotational position detection signal are synchronized and a certain period of time has elapsed, the recording start control device 47 is activated and recording is started. The radial feed device 10 is also activated. The recording start control device 47 includes a plunger solenoid 48 and a shutter 49.
The plunger solenoid 48 is configured to remove the shutter 49 from the path of the recording light beam and start recording when the plunger solenoid 48 is activated in response to the phase difference detection signal.

Next, the corrected speed detection frequency signal forming circuit 39 will be explained with reference to FIGS. 3 and 4. The speed detector 18 in Figure 3 has a duty ratio of 50% as shown in Figure 4A.
A rectangular wave output is generated according to the speed of the motor 3. Figure 4 shows the state at the start of driving the motor 3, so initially the speed detection frequency signal is not generated at a constant cycle, but when the motor 3 reaches a predetermined rotational speed, a pulse is generated at a cycle of 1H. occurs.
The speed detection frequency signal is waveform-shaped by the waveform shaping circuit 50 into a constant frequency signal having a pulse width shown in FIG. 4B.

51 is a pulse generation circuit, which sends out a subcarrier pulse of 3.58 MHz to generate a clock pulse. 52 is a 1/8 frequency divider,
Divide the 3.58MHz of the pulse generation circuit 51 into 1/8.
This provides a 447.5kHz clock pulse. 5
3 is an 8-bit counter for storing the phase difference between the speed detection frequency signal and the position detection signal. This counter 53 receives a position detection signal, a synchronization detection signal,
Flip-flops 54, 55 for control based on the speed detection frequency signal, clock pulses;
An AND gate 56 and inhibit AND gates 57, 58, 59 are provided.

When playback starts, the disk rotates and the position detection signal shown in FIG. 4E is output from the position detection device 24.
Occurs at the rate of one rotational pulse. However, since the AND gate 56 coupled to the position sensing device 24 is blocked (off) at startup, the next stage flip-flop 55 is not set. The other input of the AND gate 56 is coupled to the synchronization detection circuit 43 via the flip-flop 54, the delay circuit 33, and the drive circuit 44, so frame synchronization is detected at time _t8 as shown by the dotted line in FIG. 4D. A signal is generated, which is inputted as a set signal to the flip-flop 54 at time _t11 with a delay of T _D , and the position detection signal is not output from the AND gate 56 until the Q output of the flip-flop 54 becomes high level. . A delayed synchronization detection signal is generated at t ₁₁ ,
Once flip-flop 54 is set, the position detection signal of FIG. _4E generated at time t12 passes through AND gate 56 and sets flip-flop 55. Therefore, the Q output of the flip-flop 55 goes from a low level to a high level at time _t12 when the position detection signal is generated, and the inhibit AND gate 5
7, 58, and 59 are in a prohibited state.

The clock input terminal CK of the counter 53 is connected to the frequency divider 52 via a gate 58.
The set terminal S of the counter 53 is connected to the waveform shaping circuit 50 through the gate 57, and the reset terminal R of the counter 53 is connected to the waveform shaping circuit 50 through the gate 59. When the set terminal S is at a low level, a clock pulse is input. is enabled, and is configured to be reset when the reset terminal R is at a high level. In the circuit shown in Fig. 2, the synchronization detection signal is generated at time _t8 , and at time _t11 , when the control system has stabilized, the flip-flop 55 is set with the first position detection signal after the delayed synchronization detection signal is generated. Before time t ₁₂ , inhibit AND gates 57, 58, 5
9 is in the signal transmission state, the 8-bit counter 53 is reset by the high level of the waveform shaping signal of FIG. 4B, and the frequency divider 52 is reset during the next low level period.
clock pulses and repeat the counting as illustrated in FIG. 4C. Therefore, even at the time _t9 to _t10 immediately before the position detection signal is generated at the time _t12 , the waveform shaping signal shown in FIG. 53 is reset. When the waveform shaping output becomes low level at time _t10 , the counter 53 is controlled to a set state by the low level output of the inhibit AND gate 57, and the frequency divider 52 starts counting the clock pulses. After that,
When a position detection signal is generated at time _t12 as shown in FIG. 4E, flip-flop 55 is set;
This Q output becomes high level. Therefore, the inhibit AND gates 57, 58, and 59 are inhibited, and the counting operation of the memory counter 53 is stopped. As a result, the number of clock pulses during the period _TA from t ₁₀ to _{t 20} is stored in the counter 53.

60 is an 8-bit up/down counter whose preset terminal is connected to memory counter 5.
3, its down input terminal 61 is coupled to the output of the frequency divider 52, and its load terminal 62 is coupled to the output of the waveform shaping circuit 50. The load terminal 62 is connected to the up/down counter ₆ in response to the high level of the output of the waveform shaping circuit 50 shown in FIG. 4B.
It has a function to preset to 0. Therefore, during the period _t13 to _t14 in FIG.
The count value N _A of the memory counter 53 is written to 0. When the signal at the load terminal 62 becomes low level, it becomes a down count state and the up/down counter 60 returns to the preset count value.
The clock pulses of the frequency divider 52 are taken in such a manner that N _A is sequentially decreased. As a result, the count value of the up/down counter 60 is changed to the time point _t15 when the time T _A has elapsed from the falling time point _t14 of the waveform shaping pulse.
The count becomes zero, and a borrow output is obtained as shown in FIG. 4G. That is, at zero count, an output pulse with half the clock width is obtained. Such an operation is obtained every time a waveform shaping pulse is generated.
The corrected speed detection frequency signal shown in FIG.
This is _a frequency signal that is obtained by shifting the phase of the waveform-shaped speed detection frequency signal shown in _FIG .

Both phase comparators 32 and 38 in FIG. 1 are sample-and-hold type phase comparators, and both are constructed as shown in principle in FIG. 5. That is, a differentiating circuit DF ₁ that differentiates the reference signal, a transistor Q ₁ that is turned on by a differential pulse, a constant current source I, and a transistor Q ₁ that is charged with the current supplied from the constant current source I and generates a slope voltage. A capacitor C ₁ discharges when the sampling switch SW is on, a capacitor C ₂ holds the voltage of the capacitor C ₁ while the sampling switch SW is on, and the sampling switch SW differentiates the detected position detection signal or corrected speed detection frequency signal. Differential circuit that turns on
DF ₂ and a field effect transistor FET that outputs the voltage of capacitor C ₂ , and outputs a DC voltage corresponding to the phase difference between the reference signal and the detected frequency signal.

Next, the recording method and operation of the apparatus shown in FIG. 1 will be described. When forming a record on the disk 1, for example, the disk 1 having a photoresist layer is used.
is rotated by motor 3. At this time, the first switch circuit 21 is kept on and the second switch circuit 23 is kept off. As a result, the motor 3 and the disk 1 are speed-controlled, that is, frequency-controlled, to a constant rotational speed. At the same time, one pulse is generated from the rotational position detection device 24 for one rotation corresponding to a certain position of the disk 1, and this pulse is generated by the phase comparison circuit 31.
and becomes an input to the phase difference detection circuit 42. Further, a frame synchronization reference signal based on a vertical synchronization signal separated from the composite video signal supplied from the video signal supply circuit 8 is sent to the phase comparison circuit 32 and the synchronization detection circuit 4.
Enter 3. Even if the speed of the motor 3 is controlled by the output of the speed detection circuit 17, the phases of the frame synchronization reference signal and the rotational position detection signal do not necessarily match, so the frame is adjusted so that this phase difference becomes zero. The output voltage of the synchronous phase comparison circuit 31 is superimposed on the speed detection signal voltage, and the motor drive circuit 12
As input. As a result, control is performed such that the phases of the frame synchronization reference signal and the rotational position detection signal match, and after a little time has passed since the start of the motor 3, a synchronization detection signal is obtained from the synchronization detection circuit 43, and the first switch is activated. The circuit 21 is turned off and the second
The switch circuit 23 is turned on. Therefore, instead of the speed detection voltage, a stabilized voltage, that is, a fixed voltage, is supplied from the stabilized voltage supply circuit 22 to the motor drive circuit 12. Since the stabilizing voltage is set in advance to be substantially equal to the output voltage of the speed detection circuit 17 corresponding to a constant rotational speed in a normal state, switching of the first and second switch circuits 21 and 23 is easy. Even if this is done, disturbances in motor control will not substantially occur. Also, even if speed control by feedback is stopped,
Since the phase control based on the frame synchronization reference signal and the position detection signal is continued, the motor 3 and the disk 1 are controlled to maintain a constant rotational speed.

On the other hand, the corrected speed detection frequency signal forming circuit 39 corrects the speed detection frequency signal shown in FIG. 6D to the corrected speed detection frequency signal shown in FIG. 6E. That is, when a synchronization detection signal is generated from the synchronization detection circuit 43, it is inputted to the correction speed detection signal forming circuit 39 via the drive circuit 44 and the delay circuit 33, and in response, the correction amount is stored and the The pulse of FIG. 6D is shifted as shown in FIG. 6E so as to eliminate the phase difference, that is, the time difference T _A between the position detection signal shown in FIG. 6C and the speed detection frequency signal shown in FIG. 6D. . Note that the position detection signal in FIG.
Since it is synchronized with the frame synchronization reference signal shown in FIG. A and the horizontal synchronization reference signal shown in FIG. 6B, the corrected speed detection frequency signal is eventually synchronized with the horizontal synchronization signal. The synchronization detection output of the synchronization detection circuit 43 is sent to the first and second selection switches 3 via a delay circuit 45.
5 and 41, the second selection switch 41 is turned on instead of the first selection switch 35, and the output of the horizontal synchronization phase comparison circuit 37 is applied to the motor drive circuit 12, allowing highly accurate phase control. Move. Further, the shutter 47 is opened based on the output of the delay circuit 45, and recording using the modulated light beam is started. Also, the radial feed device 10 is activated and radial feeding is started.

The operation is exactly the same even when recording is interrupted as described above and recording is started again. Therefore, it becomes possible to record not only the vertical synchronization signal but also the horizontal synchronization signal while always maintaining a constant positional relationship with respect to the position detection signal shown in FIG. 6C before and after the interruption. Therefore, if a recording track TR is formed on the disk 1 as shown in FIG. 2, the vertical synchronizing signals V _S will be accurately arranged in a straight line regardless of interruptions in recording.

As is clear from the above, this embodiment has the following advantages.

(a) Since the corrected speed detection frequency signal forming circuit 39 is provided and controlled, the vertical synchronizing signal V _S can be aligned at a constant angular position on the disk 1 without causing a 1H deviation after recording is interrupted. Therefore, the image will not be distorted during playback.

(b) When the synchronization state is detected, first the switch circuits 21 and 23 are switched, and then the output of the delay circuit 45 is used to switch between the switches 35 and 41, so the motor control until the start of recording is performed. can be carried out smoothly.

(c) After the synchronization is detected, the stabilized voltage is supplied from the stabilized voltage supply circuit 22, so even if the detected voltage changes due to temperature changes or secular changes in the speed detection circuit 17, this will not occur. Phase control can be performed independently.

(d) Since the temperature characteristics of the stabilized voltage supply circuit 22 are set to be opposite to those of the phase comparator circuits 31 and 37 due to, for example, the characteristics of the Zener diode ZD, When the output voltage of the phase comparator circuit 31 or 37 increases, the output voltage of the stabilizing voltage supply circuit 22 decreases, the voltages cancel each other out, and no deviation in control occurs due to temperature changes. If control by the speed detection circuit 17 is continued and the specified output voltage cannot be obtained at a constant rotation speed due to a deviation due to temperature or aging, the operating point in phase control will be shifted, and as a result, the phase Misalignment occurs.

Modifications The present invention is not limited to the above-mentioned embodiments, and for example, the following modifications are possible.

(a) Disc 1 or turntable 2 is provided with two detected parts such as reflective surfaces 28 at 180 degree intervals, and the reference signal circuit 29 also generates a reference signal synchronized with the vertical synchronizing signal for each field. It's okay.

(b) Instead of aligning the detected part for detecting the rotational position with the vertical synchronizing signal recording area, for example, as shown in _FIG . It may be provided. In such a case, a phase shift circuit is provided in the reference signal circuit 29 or the rotational position detection circuit 24 or the like to electrically adjust the phases of the phase comparison circuit system and the synchronization detection circuit system. Further, the position of the reflecting surface 28a may be moved away from the vertical synchronizing signal recording area V _S by an amount corresponding to the response delay.

(c) It is applicable not only to optical recording but also to, for example, magnetic recording.

(d) Without configuring the recording start control device 38 to control the shutter 49, the light source 5 or the light modulator 6
Alternatively, a video signal supply line or the like may be controlled.

(e) The period of the horizontal synchronization reference signal may not be 1H, but may be multiple H.

[Brief explanation of drawings]

1 is a block diagram showing a recording apparatus according to an embodiment of the present invention, FIG. 2 is a plan view illustrating the disk shown in FIG. 1, and FIG. 3 is a corrected speed detection frequency signal forming circuit shown in FIG. 1. FIG. 4 is a waveform diagram showing the states of points A to G in FIG. 3, FIG. 5 is a circuit diagram illustrating the phase comparator in FIG. 1, and FIG.
The figure is a waveform diagram showing the states of points A to E in FIG. 1. DESCRIPTION OF SYMBOLS 1...Disk, 3...Motor, 18...Speed detector, 24...Position detection device, 29...Frame synchronization reference signal circuit, 36...Horizontal synchronization reference signal circuit, 3
2, 38... Phase comparator, 39... Correction speed detection frequency signal forming circuit.

Claims (1)

[Scope of Claims] 1. A disk drive motor for rotating a recording medium disk, a recording head for recording a composite video signal on the disk, and a radial direction of the disk between the disk and the recording head. a radial direction feeding device for producing relative feed of the disk; a rotational position detection device for detecting a fixed position in the circumferential direction of the disk during rotational driving from the disk or a part rotating together with the disk; a vertical or frame synchronization reference signal circuit that generates a vertical or frame synchronization reference signal synchronized with a vertical synchronization signal or frame synchronization signal of a composite video signal; and a position detection signal obtained from the rotational position detection device and the vertical or frame synchronization reference. a vertical or frame synchronization phase comparison circuit that generates a voltage corresponding to the phase difference with the signal; a motor rotation speed detector that generates a speed detection frequency signal corresponding to the rotation of the motor; and from the motor rotation speed detector. a corrected speed detection frequency signal forming circuit that forms a corrected speed detection frequency signal corrected to synchronize the obtained speed detection frequency signal with the position detection signal obtained from the rotational position detection device; a horizontal synchronization reference signal circuit that generates a horizontal synchronization reference signal synchronized with the synchronization signal; a horizontal synchronization phase comparison circuit that generates a voltage corresponding to a phase difference between the corrected speed detection frequency signal and the horizontal synchronization reference signal; a switch circuit that selectively selects the output of the vertical or frame synchronization phase comparison circuit and the output of the horizontal synchronization phase comparison circuit; and a switch circuit that selectively selects the output of the vertical or frame synchronization phase comparison circuit; and A video disc recording device comprising: a motor drive circuit that drives the motor so as to make a phase difference with a reference signal or a phase difference between the corrected speed detection frequency signal and the horizontal synchronization reference signal zero.