JPS6455652A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6455652A
JPS6455652A JP62211233A JP21123387A JPS6455652A JP S6455652 A JPS6455652 A JP S6455652A JP 62211233 A JP62211233 A JP 62211233A JP 21123387 A JP21123387 A JP 21123387A JP S6455652 A JPS6455652 A JP S6455652A
Authority
JP
Japan
Prior art keywords
given
debugging
initialization
gate circuit
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62211233A
Other languages
Japanese (ja)
Inventor
Toshiya Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62211233A priority Critical patent/JPS6455652A/en
Publication of JPS6455652A publication Critical patent/JPS6455652A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To efficiently perform the debugging processing, by controlling the initialization of a storage means in which information required for debugging processing is stored by select information set and supplied independently of a reset signal. CONSTITUTION:When the reset signal is given to a gate circuit 7, to which mask information M1-Mn indicating that initialization of debugging registers R1-Rn is inhibited are given, from the external through a reset terminal 3, an initializing signal is not given to corresponding debugging registers R1-Rn from the gate circuit 7; but when the reset signal is given to the gate circuit 7, to which mask information M1-Mn indicating that initialization of debugging registers R1-Rn is permitted are given, from the external through the reset terminal 3, the initializing signal is given to corresponding debugging registers R1-Rn from the gate circuit 7. Thus, the initialization of debugging registers due to the reset signal is inhibited to efficiently perform the debugging processing.
JP62211233A 1987-08-27 1987-08-27 Data processor Pending JPS6455652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62211233A JPS6455652A (en) 1987-08-27 1987-08-27 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62211233A JPS6455652A (en) 1987-08-27 1987-08-27 Data processor

Publications (1)

Publication Number Publication Date
JPS6455652A true JPS6455652A (en) 1989-03-02

Family

ID=16602491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62211233A Pending JPS6455652A (en) 1987-08-27 1987-08-27 Data processor

Country Status (1)

Country Link
JP (1) JPS6455652A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08185245A (en) * 1994-12-28 1996-07-16 Hewlett Packard Japan Ltd How to reset the microprocessor
US6877112B1 (en) 1999-11-05 2005-04-05 Fujitsu Limited Reset control system and method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115546A (en) * 1981-12-29 1983-07-09 Fujitsu Ltd Microcomputer incorporating hardware break pointer
JPS62127918A (en) * 1985-11-28 1987-06-10 Oki Electric Ind Co Ltd Logic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115546A (en) * 1981-12-29 1983-07-09 Fujitsu Ltd Microcomputer incorporating hardware break pointer
JPS62127918A (en) * 1985-11-28 1987-06-10 Oki Electric Ind Co Ltd Logic circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08185245A (en) * 1994-12-28 1996-07-16 Hewlett Packard Japan Ltd How to reset the microprocessor
US6877112B1 (en) 1999-11-05 2005-04-05 Fujitsu Limited Reset control system and method

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