JPS645568U - - Google Patents
Info
- Publication number
- JPS645568U JPS645568U JP9942087U JP9942087U JPS645568U JP S645568 U JPS645568 U JP S645568U JP 9942087 U JP9942087 U JP 9942087U JP 9942087 U JP9942087 U JP 9942087U JP S645568 U JPS645568 U JP S645568U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- vertical synchronization
- timing signal
- circuit
- synchronization signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Synchronizing For Television (AREA)
Description
第１図はこの考案の一実施例による垂直同期信
号分離回路を示すブロツク図、第２図ａ〜ｃは第
１図に示した垂直同期信号分離回路の各部分の信
号を示す波形図、第３図は従来の垂直同期信号分
離回路を示す回路図、第４図ａ，ｂは第３図に示
した垂直同期信号分離回路の各部分の信号を示す
波形図である。
図において、１１はモノマルチバイブレータ（
タイミング信号生成回路）、１２はＤフリツプ・
フロツプ回路（分離回路）、ＳＩは複合同期信号
、ＳＴはタイミング信号、Ｓｏ２は垂直同期信号
を示す。なお、図中、同一符号は同一、または相
当部分を示す。
FIG. 1 is a block diagram showing a vertical synchronizing signal separating circuit according to an embodiment of the invention, FIGS. 2 a to c are waveform diagrams showing signals of each part of the vertical synchronizing signal separating circuit shown in FIG. FIG. 3 is a circuit diagram showing a conventional vertical synchronization signal separation circuit, and FIGS. 4a and 4b are waveform diagrams showing signals of each part of the vertical synchronization signal separation circuit shown in FIG. 3. In the figure, 11 is a mono multivibrator (
(timing signal generation circuit), 12 is a D flip
In the flop circuit (separation circuit), SI indicates a composite synchronization signal, ST indicates a timing signal, and S o2 indicates a vertical synchronization signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
イミング信号を生成する論理回路で構成されたタ
イミング信号生成回路と、前記入力信号と前記タ
イミング信号から垂直同期信号を分離する論理回
路で構成した分離回路とを備えた垂直同期信号分
離回路。 a timing signal generation circuit configured with a logic circuit that generates a timing signal from an input signal that is a composite of horizontal and vertical synchronization signals; and a separation circuit configured with a logic circuit that separates the vertical synchronization signal from the input signal and the timing signal. Vertical synchronization signal separation circuit with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9942087U JPS645568U (en) | 1987-06-30 | 1987-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9942087U JPS645568U (en) | 1987-06-30 | 1987-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS645568U true JPS645568U (en) | 1989-01-12 |
Family
ID=31326562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9942087U Pending JPS645568U (en) | 1987-06-30 | 1987-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS645568U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0649931U (en) * | 1992-12-14 | 1994-07-08 | 株式会社光陽 | Roughness measurement gauge |
-
1987
- 1987-06-30 JP JP9942087U patent/JPS645568U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0649931U (en) * | 1992-12-14 | 1994-07-08 | 株式会社光陽 | Roughness measurement gauge |
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