JPS6458111A - Digital mixer - Google Patents

Digital mixer

Info

Publication number
JPS6458111A
JPS6458111A JP21474887A JP21474887A JPS6458111A JP S6458111 A JPS6458111 A JP S6458111A JP 21474887 A JP21474887 A JP 21474887A JP 21474887 A JP21474887 A JP 21474887A JP S6458111 A JPS6458111 A JP S6458111A
Authority
JP
Japan
Prior art keywords
fed
gate
sets
selector
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21474887A
Other languages
Japanese (ja)
Other versions
JP2625750B2 (en
Inventor
Seiichiro Iwase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62214748A priority Critical patent/JP2625750B2/en
Publication of JPS6458111A publication Critical patent/JPS6458111A/en
Application granted granted Critical
Publication of JP2625750B2 publication Critical patent/JP2625750B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Complex Calculations (AREA)
  • Analogue/Digital Conversion (AREA)
  • Studio Circuits (AREA)

Abstract

PURPOSE:To reduce the entire circuit scale by using a circuit component comprising a selector and a full adder. CONSTITUTION:The i-th bits ai, bi of input signals A, B are fed to AND gate, 11, 12 forming a selector 1, a 1st bit ki of a coefficient K is fed to the gate 11 and fed to the gate 12 with inversion. The output of the gates 11, 12 is fed to the full adder 2 through an OR gate 13. In providing n<2> sets of circuit components as shown in broken lines in figure, the mixing arithmetic operation of AK+(1-K)B is realized. Thus, in order to realize the n-bit mixer, components of n<2>+n sets of full adders and 3Xn<2> sets of AND/OR gates are used for its realization.
JP62214748A 1987-08-28 1987-08-28 Digital mixer Expired - Fee Related JP2625750B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62214748A JP2625750B2 (en) 1987-08-28 1987-08-28 Digital mixer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62214748A JP2625750B2 (en) 1987-08-28 1987-08-28 Digital mixer

Publications (2)

Publication Number Publication Date
JPS6458111A true JPS6458111A (en) 1989-03-06
JP2625750B2 JP2625750B2 (en) 1997-07-02

Family

ID=16660929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62214748A Expired - Fee Related JP2625750B2 (en) 1987-08-28 1987-08-28 Digital mixer

Country Status (1)

Country Link
JP (1) JP2625750B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6354071A (en) * 1986-08-25 1988-03-08 Hitachi Ltd Digital mixer circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6354071A (en) * 1986-08-25 1988-03-08 Hitachi Ltd Digital mixer circuit

Also Published As

Publication number Publication date
JP2625750B2 (en) 1997-07-02

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees