JPS6458114A - Flip-flop - Google Patents

Flip-flop

Info

Publication number
JPS6458114A
JPS6458114A JP62214186A JP21418687A JPS6458114A JP S6458114 A JPS6458114 A JP S6458114A JP 62214186 A JP62214186 A JP 62214186A JP 21418687 A JP21418687 A JP 21418687A JP S6458114 A JPS6458114 A JP S6458114A
Authority
JP
Japan
Prior art keywords
circuit
signal
output signal
logic amplitude
latch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62214186A
Other languages
Japanese (ja)
Other versions
JP2681937B2 (en
Inventor
Tomihiro Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62214186A priority Critical patent/JP2681937B2/en
Priority to DE19883875878 priority patent/DE3875878T2/en
Priority to EP19880114042 priority patent/EP0305941B1/en
Publication of JPS6458114A publication Critical patent/JPS6458114A/en
Application granted granted Critical
Publication of JP2681937B2 publication Critical patent/JP2681937B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To attain high speed operation by operating only a propagation signal from a 1st latch circuit to a 2nd latch circuit as a signal having a smaller logic amplitude than that of the input/output signal to/from the outside of the circuit and shifted lower. CONSTITUTION:The logic amplitude VlM of an output signal DM of a master latch circuit 95 is set to a value smaller than the logic amplitude VlS of the output signal DL of the slave latch circuit 96 and the output signal DS of the selector circuit 97, e.g., to 1/2. A resistor 42 is connected between the resistors 40, 41 and the power potential 70 in the circuit 95. Let the resistance of the resistor 42 be RCQ, then the signal DM is shifted lower by I1.RCQ. With the signal DM at 'H'. the level of a collector coupling section 32 of the circuit 96 goes to 'L', but because of the said shift, the collector potential is not lower to be saturated, resulting that the delay in the propagation time of the circuit 96 is prevented. Since the logic amplitude VlM is selected to 1/2 of the VlS, the margin is reduced, the reference potential VR1 is abolished in the circuit 96 and the inverted data signal DM given to a TR 7 is inputted instead to ensure the margin.
JP62214186A 1987-08-29 1987-08-29 Flip flop Expired - Lifetime JP2681937B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62214186A JP2681937B2 (en) 1987-08-29 1987-08-29 Flip flop
DE19883875878 DE3875878T2 (en) 1987-08-29 1988-08-29 HIGH-SPEED OPERATIONAL FLIPFLOP SUITABLE FOR IMPLEMENTATION AS AN INTEGRATED CIRCUIT.
EP19880114042 EP0305941B1 (en) 1987-08-29 1988-08-29 Flipflop which is operable at high speed and adapted to implementation as an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62214186A JP2681937B2 (en) 1987-08-29 1987-08-29 Flip flop

Publications (2)

Publication Number Publication Date
JPS6458114A true JPS6458114A (en) 1989-03-06
JP2681937B2 JP2681937B2 (en) 1997-11-26

Family

ID=16651661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62214186A Expired - Lifetime JP2681937B2 (en) 1987-08-29 1987-08-29 Flip flop

Country Status (1)

Country Link
JP (1) JP2681937B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01286511A (en) * 1988-05-13 1989-11-17 Fujitsu Ltd Master slave type flip-flop circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01286511A (en) * 1988-05-13 1989-11-17 Fujitsu Ltd Master slave type flip-flop circuit

Also Published As

Publication number Publication date
JP2681937B2 (en) 1997-11-26

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