JPS6459449A - Asynchronous signal synchronizing circuit - Google Patents

Asynchronous signal synchronizing circuit

Info

Publication number
JPS6459449A
JPS6459449A JP21599387A JP21599387A JPS6459449A JP S6459449 A JPS6459449 A JP S6459449A JP 21599387 A JP21599387 A JP 21599387A JP 21599387 A JP21599387 A JP 21599387A JP S6459449 A JPS6459449 A JP S6459449A
Authority
JP
Japan
Prior art keywords
reception
transmission
data
registers
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21599387A
Other languages
Japanese (ja)
Inventor
Masabumi Morihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21599387A priority Critical patent/JPS6459449A/en
Publication of JPS6459449A publication Critical patent/JPS6459449A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To considerably economize the amount of hardware even in case of the increase of the number of busses for control data by sharing registers for interface to the external between data transmission and reception. CONSTITUTION:When an asynchronous signal synchronizing and sending part 1 is operated in the reception mode, asynchronous reception data which is received from a device 2 through a transmission/reception part 3 is held in a data holding part 7 and is transmitted to a processor 5 synchronously with the internal clock outputted from a synchronous signal part 6. When the asynchronous signal synchronizing and sending part 1 is operated in the transmission mode, transmission data sent from the processor 5 is held in the data holding part 7 and is sent to the device 2 through the transmission/reception part 3. In this case, the data holding part 7 has registers having the same width as the bus width, and these registers are simultaneously controlled for synchronization by the clock of the synchronous signal part 6. Thus, it is sufficient if registers are extended in case of extension of the bus width.
JP21599387A 1987-08-29 1987-08-29 Asynchronous signal synchronizing circuit Pending JPS6459449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21599387A JPS6459449A (en) 1987-08-29 1987-08-29 Asynchronous signal synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21599387A JPS6459449A (en) 1987-08-29 1987-08-29 Asynchronous signal synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS6459449A true JPS6459449A (en) 1989-03-07

Family

ID=16681624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21599387A Pending JPS6459449A (en) 1987-08-29 1987-08-29 Asynchronous signal synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS6459449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5167591A (en) * 1988-05-06 1992-12-01 Ben Cowan Variable speed transmission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5167591A (en) * 1988-05-06 1992-12-01 Ben Cowan Variable speed transmission

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