JPS6460023A - Analog/digital converting circuit - Google Patents

Analog/digital converting circuit

Info

Publication number
JPS6460023A
JPS6460023A JP21503887A JP21503887A JPS6460023A JP S6460023 A JPS6460023 A JP S6460023A JP 21503887 A JP21503887 A JP 21503887A JP 21503887 A JP21503887 A JP 21503887A JP S6460023 A JPS6460023 A JP S6460023A
Authority
JP
Japan
Prior art keywords
analog
digital
signal
digital converter
alternately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21503887A
Other languages
Japanese (ja)
Inventor
Jinichi Takano
Akira Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21503887A priority Critical patent/JPS6460023A/en
Publication of JPS6460023A publication Critical patent/JPS6460023A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To simplify the circuit and to lower the costs of it by alternately switching analog signal branched and amplified respectively at a high level and a low level, digital-converting the signal by a single analog/digital converter, and obtaining the digital signal by synchronizingly adding the output. CONSTITUTION:After the analog signals are branched into the high and low levels, they are switched by a change-over switch 14, alternately inputted to an analog/digital converter 15, and converted to the digital signals. By a clock signal identical with that to operate the change-over switch 14 and its inversion signal, D flip flops 16 and 17 are alternately operated, the outputs from the analog/digital converter 15 are accumulated into the D flip flops 16 and 17, and then, they are added by an adder 18. Thus, since only one analog/digital converter is provided, the circuit can be simplified, and the costs can be lowered.
JP21503887A 1987-08-31 1987-08-31 Analog/digital converting circuit Pending JPS6460023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21503887A JPS6460023A (en) 1987-08-31 1987-08-31 Analog/digital converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21503887A JPS6460023A (en) 1987-08-31 1987-08-31 Analog/digital converting circuit

Publications (1)

Publication Number Publication Date
JPS6460023A true JPS6460023A (en) 1989-03-07

Family

ID=16665726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21503887A Pending JPS6460023A (en) 1987-08-31 1987-08-31 Analog/digital converting circuit

Country Status (1)

Country Link
JP (1) JPS6460023A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980034053A (en) * 1996-11-05 1998-08-05 이형도 Analog to Digital Inverter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980034053A (en) * 1996-11-05 1998-08-05 이형도 Analog to Digital Inverter

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