JPS6465596A - Memory - Google Patents
MemoryInfo
- Publication number
- JPS6465596A JPS6465596A JP63194683A JP19468388A JPS6465596A JP S6465596 A JPS6465596 A JP S6465596A JP 63194683 A JP63194683 A JP 63194683A JP 19468388 A JP19468388 A JP 19468388A JP S6465596 A JPS6465596 A JP S6465596A
- Authority
- JP
- Japan
- Prior art keywords
- data
- register
- input
- written
- contents
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003491 array Methods 0.000 abstract 1
- 239000002131 composite material Substances 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 230000004044 response Effects 0.000 abstract 1
Landscapes
- Digital Computer Display Output (AREA)
- Dram (AREA)
Abstract
PURPOSE: To attain efficiency in data processing by storing in a register the data that is written in a memory cell selected in arrays and writing the contents of the register or the data received by a data input device in response to a write mode signal. CONSTITUTION: A data register 8 stores the multi-data bit corresponding to the number of input in a storage device 1, and this data bit is supplied as input data in a following write cycle. A multiplexer 26 makes selections between the data supply to the data register 8 and the data supply to the data input. In addition, with a write mask register 54 arranged, writing in a memory array is inhibited for a few bits of the data register 8. The storage device 1 further contains a circuit for selectively inhibiting the use of a composite level in the final row; the contents of the data register 8 are written in a plurality of rows for each input/output; as a result, multiple bits are written in a single write cycle. Thus, data is outputted at high speed in a picture display device, with calling performance improved of the stored contents to a data processing device.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/081,926 US4961171A (en) | 1987-05-21 | 1987-08-05 | Read/write memory having an on-chip input data register |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6465596A true JPS6465596A (en) | 1989-03-10 |
Family
ID=22167287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63194683A Pending JPS6465596A (en) | 1987-08-05 | 1988-08-05 | Memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6465596A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59192285A (en) * | 1983-04-15 | 1984-10-31 | 株式会社日立製作所 | Image memory circuit |
| JPS6067989A (en) * | 1983-09-26 | 1985-04-18 | 株式会社日立製作所 | Image display circuit |
| JPS6076790A (en) * | 1983-10-03 | 1985-05-01 | 日本電信電話株式会社 | Memory |
| JPS6175390A (en) * | 1984-09-20 | 1986-04-17 | デイジタルコンピユ−タ株式会社 | Memory access circuit for bit map display device |
| JPS61130985A (en) * | 1984-11-21 | 1986-06-18 | テクトロニツクス・インコーポレイテツド | Multi-bit pixel data accumulator |
-
1988
- 1988-08-05 JP JP63194683A patent/JPS6465596A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59192285A (en) * | 1983-04-15 | 1984-10-31 | 株式会社日立製作所 | Image memory circuit |
| JPS6067989A (en) * | 1983-09-26 | 1985-04-18 | 株式会社日立製作所 | Image display circuit |
| JPS6076790A (en) * | 1983-10-03 | 1985-05-01 | 日本電信電話株式会社 | Memory |
| JPS6175390A (en) * | 1984-09-20 | 1986-04-17 | デイジタルコンピユ−タ株式会社 | Memory access circuit for bit map display device |
| JPS61130985A (en) * | 1984-11-21 | 1986-06-18 | テクトロニツクス・インコーポレイテツド | Multi-bit pixel data accumulator |
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