JPS6467652A - Cache memory eliminating data discordance - Google Patents

Cache memory eliminating data discordance

Info

Publication number
JPS6467652A
JPS6467652A JP62223866A JP22386687A JPS6467652A JP S6467652 A JPS6467652 A JP S6467652A JP 62223866 A JP62223866 A JP 62223866A JP 22386687 A JP22386687 A JP 22386687A JP S6467652 A JPS6467652 A JP S6467652A
Authority
JP
Japan
Prior art keywords
data
address
main memory
memory device
discordance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62223866A
Other languages
Japanese (ja)
Inventor
Mitsuo Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62223866A priority Critical patent/JPS6467652A/en
Publication of JPS6467652A publication Critical patent/JPS6467652A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To eliminate the discordance of data between a cache memory and a main memory device caused by an access given to the main memory device from another master, by providing an address memory means which stores an address and the decision data to decide said address is valid or invalid. CONSTITUTION:The 1st and 2nd address memory means 7 and 8 store the address given from a CPU bus 13 and the address given from a system bus 4 connected with a main memory device and another master (DMA, etc.) as well as the decision data showing whether these addresses are valid or not. When said DMA changes the data on the main memory corresponding to the address stored in the means 8, the decision data on said address is set invalid. Then the use of this data is avoided when an access is received from a CPU. Thus the CPU uses the data on the main memory device and then replaces the data on a cache memory with the data on the main memory device to secure the coincidence between both data in case another master changes the data on the main memory device to cause the discordance with the data on the cache memory.
JP62223866A 1987-09-09 1987-09-09 Cache memory eliminating data discordance Pending JPS6467652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62223866A JPS6467652A (en) 1987-09-09 1987-09-09 Cache memory eliminating data discordance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62223866A JPS6467652A (en) 1987-09-09 1987-09-09 Cache memory eliminating data discordance

Publications (1)

Publication Number Publication Date
JPS6467652A true JPS6467652A (en) 1989-03-14

Family

ID=16804934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62223866A Pending JPS6467652A (en) 1987-09-09 1987-09-09 Cache memory eliminating data discordance

Country Status (1)

Country Link
JP (1) JPS6467652A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535960B1 (en) 1994-12-12 2003-03-18 Fujitsu Limited Partitioned cache memory with switchable access paths
KR100759656B1 (en) * 2000-08-24 2007-09-17 닛토덴코 가부시키가이샤 Intraoral adhesive preparation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535960B1 (en) 1994-12-12 2003-03-18 Fujitsu Limited Partitioned cache memory with switchable access paths
KR100759656B1 (en) * 2000-08-24 2007-09-17 닛토덴코 가부시키가이샤 Intraoral adhesive preparation

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