JPS6468935A - Face-down bonding of semiconductor integrated circuit device - Google Patents

Face-down bonding of semiconductor integrated circuit device

Info

Publication number
JPS6468935A
JPS6468935A JP62225676A JP22567687A JPS6468935A JP S6468935 A JPS6468935 A JP S6468935A JP 62225676 A JP62225676 A JP 62225676A JP 22567687 A JP22567687 A JP 22567687A JP S6468935 A JPS6468935 A JP S6468935A
Authority
JP
Japan
Prior art keywords
electrode
resin layer
light sensitive
sensitive resin
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62225676A
Other languages
Japanese (ja)
Inventor
Hideto Kitakado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP62225676A priority Critical patent/JPS6468935A/en
Publication of JPS6468935A publication Critical patent/JPS6468935A/en
Pending legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase resistance against thermal stress and to increase current capacity, by forming a light sensitive resin layer on a substrate, on which an electrode is formed, forming many small holes in the resin layer, applying plating on the electrode through the light sensitive resin layer, extruding metal members out of the surface of the light sensitive resin layer, and bonding an IC chip to the electrode through the metal members. CONSTITUTION:An electrode 2 is formed on a ceramic substrate 1. A light sensitive resin layer 3 is formed on the electrode 2. Many small holes 4 are formed in the light sensitive resin layer by photoengraving. Then the light sensitive resin layer 3 is used as a mask, and plating is applied on the electrode 2. Metal members 5, which are formed by plating, are extending along the small holes 4 in the light sensitive resin layer 3 from the surface of the electrode 2. When the light sensitive resin metal members 5 are made to extend by 1-2mum from the surface of the light sensitive resin layer 3, the plating is stopped. Then, an IC chip 6 is aligned with the electrode 2. A bump 7 of the IC chip 6 and the metal members 5, which are formed on the electrode 2 by plating, are bonded by a thermocompression bonding method or an ultrasonic wave bonding method.
JP62225676A 1987-09-09 1987-09-09 Face-down bonding of semiconductor integrated circuit device Pending JPS6468935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62225676A JPS6468935A (en) 1987-09-09 1987-09-09 Face-down bonding of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62225676A JPS6468935A (en) 1987-09-09 1987-09-09 Face-down bonding of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6468935A true JPS6468935A (en) 1989-03-15

Family

ID=16833036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62225676A Pending JPS6468935A (en) 1987-09-09 1987-09-09 Face-down bonding of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6468935A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19937213B4 (en) * 1998-08-06 2004-11-04 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Liquid crystal display and method for mounting a liquid crystal display
JP2005526374A (en) * 2001-08-03 2005-09-02 シュラムバーガー システムズ Method for enabling electronic and mechanical connection between an electrical device and a surface equipped with a contact pad
KR100585104B1 (en) * 2003-10-24 2006-05-30 삼성전자주식회사 Manufacturing method of ultra thin flip chip package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19937213B4 (en) * 1998-08-06 2004-11-04 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Liquid crystal display and method for mounting a liquid crystal display
JP2005526374A (en) * 2001-08-03 2005-09-02 シュラムバーガー システムズ Method for enabling electronic and mechanical connection between an electrical device and a surface equipped with a contact pad
KR100585104B1 (en) * 2003-10-24 2006-05-30 삼성전자주식회사 Manufacturing method of ultra thin flip chip package

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