JPS6470819A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS6470819A JPS6470819A JP62228152A JP22815287A JPS6470819A JP S6470819 A JPS6470819 A JP S6470819A JP 62228152 A JP62228152 A JP 62228152A JP 22815287 A JP22815287 A JP 22815287A JP S6470819 A JPS6470819 A JP S6470819A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- inverter
- connector
- held
- cable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Accessory Devices And Overall Control Thereof (AREA)
Abstract
PURPOSE:To effectively prevent the generation of useless power consumption by connecting a feed control means for feeding current to a buffer circuit only when a cable is connected to a connector. CONSTITUTION:An input terminal of an inverter 16 is connected to an ground terminal 12a of the connector 12 and a ground voltage is applied to the terminal 12a when the cable connected to an external device such as a printer is connected to the terminal 12a. An output terminal of an inverter 16 is connected to a base terminal of a switching transistor (TR) 14 through a resistor R2. When the cable for connecting a data processor 10 to the external device such as a printer is not connected to the connector 12, its ground terminal 12a is in a floated state and its voltage is held at the value of about +5 volt. Thereby, the input of the inverter 16 is held at the high state and a low output is supplied to the base terminal of the TR 14. Since the TR 14 is held at a non-conductive state and no current is fed to the buffer circuit 13, power consumption is not generated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62228152A JPS6470819A (en) | 1987-09-11 | 1987-09-11 | Data processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62228152A JPS6470819A (en) | 1987-09-11 | 1987-09-11 | Data processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6470819A true JPS6470819A (en) | 1989-03-16 |
Family
ID=16872040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62228152A Pending JPS6470819A (en) | 1987-09-11 | 1987-09-11 | Data processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6470819A (en) |
-
1987
- 1987-09-11 JP JP62228152A patent/JPS6470819A/en active Pending
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