JPS647130A - Instruction prefetch method for memory system - Google Patents

Instruction prefetch method for memory system

Info

Publication number
JPS647130A
JPS647130A JP62162752A JP16275287A JPS647130A JP S647130 A JPS647130 A JP S647130A JP 62162752 A JP62162752 A JP 62162752A JP 16275287 A JP16275287 A JP 16275287A JP S647130 A JPS647130 A JP S647130A
Authority
JP
Japan
Prior art keywords
instruction
jump
register
address
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62162752A
Other languages
Japanese (ja)
Inventor
Osamu Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62162752A priority Critical patent/JPS647130A/en
Publication of JPS647130A publication Critical patent/JPS647130A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the time loss due to success in jump at the time of execution of a conditional jump instruction by providing a jump register in which the address after success in conditional jump is stored, a prefetch register in which the next instruction address is stored, and a quick buffer memory. CONSTITUTION:When a conditional jump signal 48 from a processor 8 comes, the address of a prefetch register 10 and that of a jump register 12 are distributed to an external memory 2 and a buffer memory by this information and access is performed. If the conditional jump signal does not come, the instruction address from the prefetch register 10 is outputted to the external memory 2 and the buffer memory 4 and access is performed. When an instruction to be executed exists in the buffer memory 4, its instruction data is selected and outputted to the processor 8 by an instruction selector 16; but if it does not exist there, instruction data from the external memory 2 is outputted to the processor 8.
JP62162752A 1987-06-30 1987-06-30 Instruction prefetch method for memory system Pending JPS647130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162752A JPS647130A (en) 1987-06-30 1987-06-30 Instruction prefetch method for memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162752A JPS647130A (en) 1987-06-30 1987-06-30 Instruction prefetch method for memory system

Publications (1)

Publication Number Publication Date
JPS647130A true JPS647130A (en) 1989-01-11

Family

ID=15760581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162752A Pending JPS647130A (en) 1987-06-30 1987-06-30 Instruction prefetch method for memory system

Country Status (1)

Country Link
JP (1) JPS647130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001216152A (en) * 2000-01-28 2001-08-10 Rooran:Kk Logical integrated circuit and computer readable recording medium in which source of its cpu core is recorded

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001216152A (en) * 2000-01-28 2001-08-10 Rooran:Kk Logical integrated circuit and computer readable recording medium in which source of its cpu core is recorded

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