JPS647134A - Logic simulation method - Google Patents

Logic simulation method

Info

Publication number
JPS647134A
JPS647134A JP16275387A JP16275387A JPS647134A JP S647134 A JPS647134 A JP S647134A JP 16275387 A JP16275387 A JP 16275387A JP 16275387 A JP16275387 A JP 16275387A JP S647134 A JPS647134 A JP S647134A
Authority
JP
Japan
Prior art keywords
event
evaluation
queue
state
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16275387A
Other languages
Japanese (ja)
Inventor
Masahide Sugano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16275387A priority Critical patent/JPS647134A/en
Publication of JPS647134A publication Critical patent/JPS647134A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

PURPOSE:To improve the controllability and to simplify processing procedures by providing an element table with event flags and an evaluation flag and using them to perform function operations related to the initialization of event flags and calculation of states of output terminals of logic elements. CONSTITUTION:First, the event at a prescribed time is taken out from an event queue, and a state 2b of a pertinent output terminal is updated. The fan out is read out from a connection table to update the state of the input terminal of the fan out destination. When an evaluation flag 2d is in the reset state, all event flags 2c are reset and the evaluation flag is set, and the element number is inserted to an evaluation queue. Next, the element number is taken out from the evaluation queue. Required information is read from the element table to calculate the state of the output terminal, and an event is generated and is inserted to the event queue if the event occurs. The evaluation flag 2d of this logic element is reset.
JP16275387A 1987-06-30 1987-06-30 Logic simulation method Pending JPS647134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16275387A JPS647134A (en) 1987-06-30 1987-06-30 Logic simulation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16275387A JPS647134A (en) 1987-06-30 1987-06-30 Logic simulation method

Publications (1)

Publication Number Publication Date
JPS647134A true JPS647134A (en) 1989-01-11

Family

ID=15760600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16275387A Pending JPS647134A (en) 1987-06-30 1987-06-30 Logic simulation method

Country Status (1)

Country Link
JP (1) JPS647134A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0488564A (en) * 1990-08-01 1992-03-23 Nishimura Giken:Kk Verifier for integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0488564A (en) * 1990-08-01 1992-03-23 Nishimura Giken:Kk Verifier for integrated circuit

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