JPS647135A - System for evaluating level of electronic computer system - Google Patents

System for evaluating level of electronic computer system

Info

Publication number
JPS647135A
JPS647135A JP62163762A JP16376287A JPS647135A JP S647135 A JPS647135 A JP S647135A JP 62163762 A JP62163762 A JP 62163762A JP 16376287 A JP16376287 A JP 16376287A JP S647135 A JPS647135 A JP S647135A
Authority
JP
Japan
Prior art keywords
simulator
control means
program
communication control
leading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62163762A
Other languages
Japanese (ja)
Inventor
Mitsue Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62163762A priority Critical patent/JPS647135A/en
Publication of JPS647135A publication Critical patent/JPS647135A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To evaluate various program groups and function specifications of each device with the whole of a system by constituting the system of plural software simulators, which simulate functions and operations of respective devices in the system, and an inter-simulator communication control means. CONSTITUTION:With respect to simulators, the OS leading processing program on a simulator 3 reads out an OS start up processing program from a file, where OS images are stored, and uses an inter-simulator communication control means 4 to send this program to a simulator 1 after checking the normalcy, and the simulator 1 stores this program in its own main storage device simulation area. The OS leading processing on the simulator 1 uses the intersimulator communication control means 4 to inform the start of OS leading edge to the OS leading processing program on the simulator 3 in case of starting execution, and thereafter, the inter-simulator communication control means 4 is used to inform the completion of OS leading edge to the OS leading processing program when OS leading edge is completed.
JP62163762A 1987-06-29 1987-06-29 System for evaluating level of electronic computer system Pending JPS647135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62163762A JPS647135A (en) 1987-06-29 1987-06-29 System for evaluating level of electronic computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62163762A JPS647135A (en) 1987-06-29 1987-06-29 System for evaluating level of electronic computer system

Publications (1)

Publication Number Publication Date
JPS647135A true JPS647135A (en) 1989-01-11

Family

ID=15780223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62163762A Pending JPS647135A (en) 1987-06-29 1987-06-29 System for evaluating level of electronic computer system

Country Status (1)

Country Link
JP (1) JPS647135A (en)

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