JPS647143A - Write back system for cache system - Google Patents

Write back system for cache system

Info

Publication number
JPS647143A
JPS647143A JP62162126A JP16212687A JPS647143A JP S647143 A JPS647143 A JP S647143A JP 62162126 A JP62162126 A JP 62162126A JP 16212687 A JP16212687 A JP 16212687A JP S647143 A JPS647143 A JP S647143A
Authority
JP
Japan
Prior art keywords
link
write
timer
control
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62162126A
Other languages
Japanese (ja)
Inventor
Shizuo Kanbayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP62162126A priority Critical patent/JPS647143A/en
Publication of JPS647143A publication Critical patent/JPS647143A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To interrupt a power source approximately simultaneously with the end of operation by giving priority to data transfer to a memory and writing back a link in order with a timer while successively returning the control to the link. CONSTITUTION:When data is transferred from a disk by direct memory access, it is decided whether this data exists in the link or not; and if it does not exist there, the control is returned to he write link because the action of a cache is unnecessary. If data exists in the link, a flag is set, and it is decided whether the timer is in course of write or not. If the timer is in course of write, an ineffective flag in the link is set and the control is returned to the write link. If the timer is not in course of write, it is decided whether an error flag is set or not, and the error processing is performed if the error flag is set, but the control is returned to the write link after the link is made empty if the error flag is not set.
JP62162126A 1987-06-29 1987-06-29 Write back system for cache system Pending JPS647143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162126A JPS647143A (en) 1987-06-29 1987-06-29 Write back system for cache system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162126A JPS647143A (en) 1987-06-29 1987-06-29 Write back system for cache system

Publications (1)

Publication Number Publication Date
JPS647143A true JPS647143A (en) 1989-01-11

Family

ID=15748535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162126A Pending JPS647143A (en) 1987-06-29 1987-06-29 Write back system for cache system

Country Status (1)

Country Link
JP (1) JPS647143A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1010922C2 (en) * 1998-12-30 2000-07-03 Roba Handelmaatschappij B V Modular pallet system for use with fork lift trucks has demountable junctions between upper and lower cross beams and is used for stacked sheets of steel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1010922C2 (en) * 1998-12-30 2000-07-03 Roba Handelmaatschappij B V Modular pallet system for use with fork lift trucks has demountable junctions between upper and lower cross beams and is used for stacked sheets of steel

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