JPS647201A - Sequence debugging system - Google Patents

Abstract

PURPOSE:To shorten a debugging working time and to improve a working efficiency by stepping back to a certain past point of time, reproducing a condition, re-executing the input of a sequence after the point of time and replaying after the point of time in a debugging working. CONSTITUTION:An external input signal Si is sequentially stored to an input signal preserving buffer means 8 times synchronized to the period of which is settable, an input condition, an internal condition output condition and the period of on step-back clock CPS are stored into a condition preserving buffer means 10 times synchronized with the step-back clock CPS which frequency divides the master clock CP. In the replaying mode, the contents of the condition preserving buffer means 10 are set to an input condition holding means 2, an internal condition holding means 3, an output condition holding means 5 and a aster clock generating means 6 in the unit of the stepback clock CPS, the contents of the input signal preserving buffer means 8 are inputted to the input condition holding means 2 and the later sequence is reproduced. Thus, the time and manday can be shortened.