JPS6472085A - Method for testing semiconductor integrated circuit - Google Patents

Method for testing semiconductor integrated circuit

Info

Publication number
JPS6472085A
JPS6472085A JP62228532A JP22853287A JPS6472085A JP S6472085 A JPS6472085 A JP S6472085A JP 62228532 A JP62228532 A JP 62228532A JP 22853287 A JP22853287 A JP 22853287A JP S6472085 A JPS6472085 A JP S6472085A
Authority
JP
Japan
Prior art keywords
pattern
signals
ffs
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62228532A
Other languages
Japanese (ja)
Inventor
Takeyoshi Uchibori
Katsuhiko Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62228532A priority Critical patent/JPS6472085A/en
Publication of JPS6472085A publication Critical patent/JPS6472085A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To easily perform a dynamic function test for a semiconductor integrated circuit by generating a test pattern in which signals are switched simultaneously targeted for the logic circuit of the semiconductor integrated circuit. CONSTITUTION:Clock signals C1 and C2 are impressed on FFs 21-24 at the same timing, and the FFs 21-24 are changed at the same time. Next, the pattern of the output signals of combination circuit net-works 31 and 32 is decided by back trace so as to set the combination of the output values of the FFs 21-24 at 11 to perform the simultaneous switching of the FFs. Similarly, the pattern of input signals i0 and i0' so as to set the combination of the output values of the FFs at 000 is decided. In such a way, a pair of test pattern data for the simultaneous switching can be decided. The pattern of the signals i0 and i0' is impressed on the semiconductor integrated circuit 12 to be tested so as to set the logic result of the pattern on each FF at respective timing of the signals C1 and C2. And by deciding the pattern of the signals i0 and i0' by changing the combination of input data for each FF from the circuit networks 31 and 32, it is possible to perform the test the circuit 12 by a simultaneous switching test pattern.
JP62228532A 1987-09-14 1987-09-14 Method for testing semiconductor integrated circuit Pending JPS6472085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62228532A JPS6472085A (en) 1987-09-14 1987-09-14 Method for testing semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62228532A JPS6472085A (en) 1987-09-14 1987-09-14 Method for testing semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6472085A true JPS6472085A (en) 1989-03-16

Family

ID=16877882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62228532A Pending JPS6472085A (en) 1987-09-14 1987-09-14 Method for testing semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6472085A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100912847B1 (en) * 2000-06-22 2009-08-18 퀄컴 인코포레이티드 Diagnostics and via reliability with E-beam probing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100912847B1 (en) * 2000-06-22 2009-08-18 퀄컴 인코포레이티드 Diagnostics and via reliability with E-beam probing

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