JPS647348U - - Google Patents
Info
- Publication number
- JPS647348U JPS647348U JP10199687U JP10199687U JPS647348U JP S647348 U JPS647348 U JP S647348U JP 10199687 U JP10199687 U JP 10199687U JP 10199687 U JP10199687 U JP 10199687U JP S647348 U JPS647348 U JP S647348U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- main memory
- microcomputer
- malfunction
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000007257 malfunction Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案の一実施例を示すブロツク図で
ある。
１……ＣＰＵ、２……主メモリ、３……補助メ
モリ、４……誤動作検知部、５，６……フリツプ
フロツプ、１１……アドレスバス、１２……デー
タバス、１３，１４……ストローブ信号、１５，
１６……動作データ信号。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1... CPU, 2... Main memory, 3... Auxiliary memory, 4... Malfunction detection section, 5, 6... Flip-flop, 11... Address bus, 12... Data bus, 13, 14... Strobe signal ,15,
16...Operation data signal.
Claims (1)
と、アドレスバスおよびデータバスを介して前記
ＣＰＵに接続した主メモリとを有するマイクロコ
ンピユータにおいて、 前記アドレスバスを介してＣＰＵに接続し、前
記主メモリのアドレス空間と同一のアドレス空間
を有し、インストラクシヨンと書き込み可のデー
タを区別するフラグを記憶した補助メモリと、 インストラクシヨンフエツチサイクルまたはメ
モリ書き込みサイクルにおいて、前記ＣＰＵが出
力するストローブ信号と前記補助メモリに記憶し
た前記フラグとの不一致を検出して前記ＣＰＵの
誤動作を検知する検知部とを具備したことを特徴
とするマイクロコンピユータの誤動作検知装置。[Scope of claim for utility model registration] CPU that executes instructions and performs various arithmetic processing
and a main memory connected to the CPU via an address bus and a data bus, the microcomputer having a main memory connected to the CPU via the address bus and having the same address space as the address space of the main memory, An auxiliary memory that stores a flag that distinguishes between instructions and writable data; and a mismatch between the strobe signal output by the CPU and the flag stored in the auxiliary memory during an instruction fetch cycle or memory write cycle. A malfunction detection device for a microcomputer, comprising: a detection section that detects a malfunction of the CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10199687U JPS647348U (en) | 1987-07-01 | 1987-07-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10199687U JPS647348U (en) | 1987-07-01 | 1987-07-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS647348U true JPS647348U (en) | 1989-01-17 |
Family
ID=31331499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10199687U Pending JPS647348U (en) | 1987-07-01 | 1987-07-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS647348U (en) |
-
1987
- 1987-07-01 JP JP10199687U patent/JPS647348U/ja active Pending
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