JPS647368A - Periodic noise removing device - Google Patents

Periodic noise removing device

Info

Publication number
JPS647368A
JPS647368A JP16287487A JP16287487A JPS647368A JP S647368 A JPS647368 A JP S647368A JP 16287487 A JP16287487 A JP 16287487A JP 16287487 A JP16287487 A JP 16287487A JP S647368 A JPS647368 A JP S647368A
Authority
JP
Japan
Prior art keywords
signal
clock
converter
fsp2
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16287487A
Other languages
Japanese (ja)
Inventor
Teruo Itami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba AVE Co Ltd
Original Assignee
Toshiba Corp
Toshiba Audio Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Audio Video Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP16287487A priority Critical patent/JPS647368A/en
Publication of JPS647368A publication Critical patent/JPS647368A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Abstract

PURPOSE:To attain the restoration of a high frequency component of a signal without incurring complicated means or increase in the circuit scale by adopting the constitution such that a signal for a prescribed period before and after a noise part is sampled by a higher frequency than that for other period. CONSTITUTION:An audio signal lead to terminals 12, 13 is given to an A/D converter 14. The converter 14 uses a sampling clock SP outputted from a switch 15 to obtain a digital signal. The clock SP is obtained by using a control signal SEL obtained from a timing signal generating circuit 16 so as to select at a switch 15 sampling clocks SP1, SP2 given from the circuit 16. The frequencies Fsp1, Fsp2 of the clocks SP1, SP2 are selected, e.g., as Fsp2=1.5Fsp1. The signal SEL selects the clock SP2 for a prescribed period before and after the audio head switching and gives it to the converter 14. In selecting the clock in this way, the increase in the processing circuits for timing matching is minimized.
JP16287487A 1987-06-30 1987-06-30 Periodic noise removing device Pending JPS647368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16287487A JPS647368A (en) 1987-06-30 1987-06-30 Periodic noise removing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16287487A JPS647368A (en) 1987-06-30 1987-06-30 Periodic noise removing device

Publications (1)

Publication Number Publication Date
JPS647368A true JPS647368A (en) 1989-01-11

Family

ID=15762909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16287487A Pending JPS647368A (en) 1987-06-30 1987-06-30 Periodic noise removing device

Country Status (1)

Country Link
JP (1) JPS647368A (en)

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