JPS6473743A - Method of filling through hole and semiconductor device using same - Google Patents
Method of filling through hole and semiconductor device using sameInfo
- Publication number
- JPS6473743A JPS6473743A JP22952687A JP22952687A JPS6473743A JP S6473743 A JPS6473743 A JP S6473743A JP 22952687 A JP22952687 A JP 22952687A JP 22952687 A JP22952687 A JP 22952687A JP S6473743 A JPS6473743 A JP S6473743A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- substrate
- layer
- conducting layer
- conductive substance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000126 substance Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 230000003416 augmentation Effects 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000000903 blocking effect Effects 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 238000005121 nitriding Methods 0.000 abstract 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To give barrier properties for blocking the counter diffusion of a substance constituting a metallic wiring with a base part by a method wherein a conductive substance is selectively deposited in the interior of a penetrated hole formed in an insulating film and this conductive substance is nitrided or silicified. CONSTITUTION:A penetrated hole is formed in an insulating film 7 formed on a single crystal Si substrate 1 and thereafter, a natural oxide film 11 remains. Then, this film 11 is removed to expose the clean surface of the substrate 1 on the bottom part of the hole 8. Then, a first conducting layer 10a is selectively formed on the surface, which is exposed on the bottom part of the hole 8, of the substrate 1. Then, by silicifying or nitriding the layer 10a, a silicified or nitrided first conducting layer 10b is formed. After that, a second conducting layer 10c is formed on the layer 10b. Thereby, an augmentation in the contact resistance between the deposited conductive substance and the substrate 1, a reduction in a selectivity at the time of deposition and so on can be prevented.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22952687A JPS6473743A (en) | 1987-09-16 | 1987-09-16 | Method of filling through hole and semiconductor device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22952687A JPS6473743A (en) | 1987-09-16 | 1987-09-16 | Method of filling through hole and semiconductor device using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6473743A true JPS6473743A (en) | 1989-03-20 |
Family
ID=16893550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22952687A Pending JPS6473743A (en) | 1987-09-16 | 1987-09-16 | Method of filling through hole and semiconductor device using same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6473743A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160273A (en) * | 1991-12-05 | 1993-06-25 | Sharp Corp | Contact plug of semiconductor device and formation thereof, and multilayer wiring of semiconductor device and formation thereof |
-
1987
- 1987-09-16 JP JP22952687A patent/JPS6473743A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160273A (en) * | 1991-12-05 | 1993-06-25 | Sharp Corp | Contact plug of semiconductor device and formation thereof, and multilayer wiring of semiconductor device and formation thereof |
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