JPS6473820A - Majority logic circuit - Google Patents

Majority logic circuit

Info

Publication number
JPS6473820A
JPS6473820A JP23026687A JP23026687A JPS6473820A JP S6473820 A JPS6473820 A JP S6473820A JP 23026687 A JP23026687 A JP 23026687A JP 23026687 A JP23026687 A JP 23026687A JP S6473820 A JPS6473820 A JP S6473820A
Authority
JP
Japan
Prior art keywords
shift register
majority logic
data
count value
counted result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23026687A
Other languages
Japanese (ja)
Other versions
JPH0797743B2 (en
Inventor
Yasuaki Takahara
Shigeyuki Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23026687A priority Critical patent/JPH0797743B2/en
Publication of JPS6473820A publication Critical patent/JPS6473820A/en
Publication of JPH0797743B2 publication Critical patent/JPH0797743B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Logic Circuits (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To obtain a majority logic to data connected to (2<k+1>-3) by using (k) sets of shift registers and to remarkably reduce the number of shift registers, by constituting a circuit so that the majority logic can be obtained by a count value stored in the shift register. CONSTITUTION:An adder means 2 counts for number of '1' or '0' at every bit of the same rank of sent connected data. A counted result to every time is stored in the shift register of (m) stages instead of the previous counted result. The counted result is (m) stage-shifted further at the shift register 1, and set as the initial value of the adder means again. The shift register is initialized to (s-n) by an initialization means at a time to start data transfer, and since a count operation is prohibited when a count value arrives at (s) by the function of detecting means 3 and a prohibiting means 4, the count value is held at (s) when the number of '1's or '0's in (2n-1) connected data exceeds (n). Therefore, it is possible to obtain the majority logic by checking whether or not the value stored in the shift register is (s) after receiving all data.
JP23026687A 1987-09-14 1987-09-14 Majority logic circuit Expired - Fee Related JPH0797743B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23026687A JPH0797743B2 (en) 1987-09-14 1987-09-14 Majority logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23026687A JPH0797743B2 (en) 1987-09-14 1987-09-14 Majority logic circuit

Publications (2)

Publication Number Publication Date
JPS6473820A true JPS6473820A (en) 1989-03-20
JPH0797743B2 JPH0797743B2 (en) 1995-10-18

Family

ID=16905106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23026687A Expired - Fee Related JPH0797743B2 (en) 1987-09-14 1987-09-14 Majority logic circuit

Country Status (1)

Country Link
JP (1) JPH0797743B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005079788A (en) * 2003-08-29 2005-03-24 Hitachi Kokusai Electric Inc Optical digital transmission device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005079788A (en) * 2003-08-29 2005-03-24 Hitachi Kokusai Electric Inc Optical digital transmission device

Also Published As

Publication number Publication date
JPH0797743B2 (en) 1995-10-18

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees