JPS6473830A - Parallel-serial converting circuit - Google Patents

Parallel-serial converting circuit

Info

Publication number
JPS6473830A
JPS6473830A JP22954687A JP22954687A JPS6473830A JP S6473830 A JPS6473830 A JP S6473830A JP 22954687 A JP22954687 A JP 22954687A JP 22954687 A JP22954687 A JP 22954687A JP S6473830 A JPS6473830 A JP S6473830A
Authority
JP
Japan
Prior art keywords
parallel
data
serial
input control
dlmn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22954687A
Other languages
Japanese (ja)
Inventor
Hiroshi Taira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22954687A priority Critical patent/JPS6473830A/en
Publication of JPS6473830A publication Critical patent/JPS6473830A/en
Pending legal-status Critical Current

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  • Communication Control (AREA)

Abstract

PURPOSE:To heighten output efficiency in parallel-serial conversion, by inputting parallel data to a shift register in each stage selectively in order, and afterwards, enabling a series of those input data to be outputted serially. CONSTITUTION:Data latch circuits DL11-DLmn constitute shift registers SFTR 1-SFTRm of parallel-in and serial-out format at every stage, respectively. To the serial data input control terminals C of the data latch circuits DL11-DLmn, a serial input control clock SCLK is supplied, and to the parallel data input control terminals PS, parallel input control clock signals PCLK 1-PCLKm are supplied. In such a way, it is possible to latch the parallel data by each of the shift registers SFTR1-SFTRm individually, and the data latch circuits DL11-DLmn are cascade-connected, then, shift control can be applied by a common serial input control clock signal CLK.
JP22954687A 1987-09-16 1987-09-16 Parallel-serial converting circuit Pending JPS6473830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22954687A JPS6473830A (en) 1987-09-16 1987-09-16 Parallel-serial converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22954687A JPS6473830A (en) 1987-09-16 1987-09-16 Parallel-serial converting circuit

Publications (1)

Publication Number Publication Date
JPS6473830A true JPS6473830A (en) 1989-03-20

Family

ID=16893860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22954687A Pending JPS6473830A (en) 1987-09-16 1987-09-16 Parallel-serial converting circuit

Country Status (1)

Country Link
JP (1) JPS6473830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0397358A1 (en) * 1989-04-27 1990-11-14 Nec Corporation Parallel to serial converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0397358A1 (en) * 1989-04-27 1990-11-14 Nec Corporation Parallel to serial converter
EP0397358B1 (en) * 1989-04-27 1996-03-13 Nec Corporation Parallel to serial converter

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