JPS6473877A - Moving image processor - Google Patents

Moving image processor

Info

Publication number
JPS6473877A
JPS6473877A JP23148387A JP23148387A JPS6473877A JP S6473877 A JPS6473877 A JP S6473877A JP 23148387 A JP23148387 A JP 23148387A JP 23148387 A JP23148387 A JP 23148387A JP S6473877 A JPS6473877 A JP S6473877A
Authority
JP
Japan
Prior art keywords
common processing
input
output bus
control
moving image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23148387A
Other languages
Japanese (ja)
Inventor
Yukio Endo
Hidenobu Harasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23148387A priority Critical patent/JPS6473877A/en
Publication of JPS6473877A publication Critical patent/JPS6473877A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To efficiently realize the common processing of a quantization processing, etc., by constituting a parallel multi-processor consisting of one stage to utilize an input/output bus between each unit processor in a video conference system, etc., and connecting a common processing circuit in a dedicated quantizer. etc., to the input/output bus. CONSTITUTION:The common processing circuit 4 performs the common processing of a signal transmitted via the output bus 102 according to a prescribed rule. An image memory 5 is a storage circuit of firstin/first-out, and it supplies image data of several scanning lines to moving image input buses 100 and 101 sequentially by the control of a control signal 106 from a control circuit 6, meanwhile, writes image data of several scanning lines transmitted from each of the unit processors 1, 2, and 3 via a moving image output bus 102 sequentially. The control circuit 8 performs input/output control for the above stated quantizer 4 and the image memory 5 and outputs a fetch start signal 103 and an output start signal 104 for each of the unit processors 1, 2, and 3, for which detail is described later.
JP23148387A 1987-09-14 1987-09-14 Moving image processor Pending JPS6473877A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23148387A JPS6473877A (en) 1987-09-14 1987-09-14 Moving image processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23148387A JPS6473877A (en) 1987-09-14 1987-09-14 Moving image processor

Publications (1)

Publication Number Publication Date
JPS6473877A true JPS6473877A (en) 1989-03-20

Family

ID=16924200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23148387A Pending JPS6473877A (en) 1987-09-14 1987-09-14 Moving image processor

Country Status (1)

Country Link
JP (1) JPS6473877A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134357A (en) * 1982-02-03 1983-08-10 Hitachi Ltd Array processor
JPS60159973A (en) * 1984-01-31 1985-08-21 Toshiba Corp Picture processing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134357A (en) * 1982-02-03 1983-08-10 Hitachi Ltd Array processor
JPS60159973A (en) * 1984-01-31 1985-08-21 Toshiba Corp Picture processing device

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