JPS647435U - - Google Patents
Info
- Publication number
- JPS647435U JPS647435U JP10227787U JP10227787U JPS647435U JP S647435 U JPS647435 U JP S647435U JP 10227787 U JP10227787 U JP 10227787U JP 10227787 U JP10227787 U JP 10227787U JP S647435 U JPS647435 U JP S647435U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- ary
- outputs
- ring counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Switches Operated By Changes In Physical Conditions (AREA)
Description
第１図は、この考案の一実施例を示す多光軸光
電スイツチの発光回路装置の回路接続図、第２図
は、同回路装置の動作を説明するためのクロツク
信号である。
１：リセツト信号発生回路、２，２２，３２：
リングカウンタ、１０：主回路基板、２０，３０
：副回路基板、２１，３１：論理積回路、Ｌ１，
Ｌ２……Ｌ１２：発光素子。
FIG. 1 is a circuit connection diagram of a light emitting circuit device of a multi-optical axis photoelectric switch showing an embodiment of this invention, and FIG. 2 is a clock signal for explaining the operation of the circuit device. 1: Reset signal generation circuit, 2, 22, 32:
Ring counter, 10: Main circuit board, 20, 30
: Sub circuit board, 21, 31: AND circuit, L 1 ,
L2 ... L12 : Light emitting element.
Claims (1)
記主回路部は、クロツク源よりのクロツクパルス
を受けて、ｎ＋１個のパルスでカウントアツプ出
力を出してホールドするｎ進のリングカウンタと
、このリングカウンタのｎ進出力により、順次点
灯される発光素子と、所定時間以上クロツク信号
が入力されないと、リセツト信号を出力するリセ
ツト信号発生回路からなり、前記副回路部はクロ
ツク信号と前段のリングカウンタのカウントアツ
プ出力を入力に受ける論理積回路と、この論理積
回路の出力を受けてｎ進の個別出力を出すｎ進の
リングカウンタと、このリングカウンタのｎ進出
力により順次点灯される発光素子とからなること
を特徴とする多光軸光電スイツチの発光回路装置
。 It consists of a main circuit section and one or more sub-circuit sections, and the main circuit section includes an n-ary ring counter that receives clock pulses from a clock source and outputs and holds a count-up output with n+1 pulses; It consists of light emitting elements that are turned on in sequence according to the n-digit output of this ring counter, and a reset signal generation circuit that outputs a reset signal if a clock signal is not input for a predetermined period of time. An AND circuit that receives the count-up output of the counter as an input, an N-ary ring counter that receives the output of this AND circuit and outputs individual n-ary outputs, and a light emitting light that is sequentially lit by the n-ary output of this ring counter. 1. A light emitting circuit device for a multi-optical axis photoelectric switch, characterized by comprising a multi-optical axis photoelectric switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10227787U JPS647435U (en) | 1987-07-02 | 1987-07-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10227787U JPS647435U (en) | 1987-07-02 | 1987-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS647435U true JPS647435U (en) | 1989-01-17 |
Family
ID=31332041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10227787U Pending JPS647435U (en) | 1987-07-02 | 1987-07-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS647435U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH053320U (en) * | 1991-02-19 | 1993-01-19 | 操二 小林 | Traffic sign |
-
1987
- 1987-07-02 JP JP10227787U patent/JPS647435U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH053320U (en) * | 1991-02-19 | 1993-01-19 | 操二 小林 | Traffic sign |
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