JPS6474637A - Debugging control circuit - Google Patents

Debugging control circuit

Info

Publication number
JPS6474637A
JPS6474637A JP62233130A JP23313087A JPS6474637A JP S6474637 A JPS6474637 A JP S6474637A JP 62233130 A JP62233130 A JP 62233130A JP 23313087 A JP23313087 A JP 23313087A JP S6474637 A JPS6474637 A JP S6474637A
Authority
JP
Japan
Prior art keywords
debugging
logical device
order
signal
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62233130A
Other languages
Japanese (ja)
Inventor
Saburo Otaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62233130A priority Critical patent/JPS6474637A/en
Publication of JPS6474637A publication Critical patent/JPS6474637A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To improve the efficiency of debugging work by storing plural conditions corresponding to operation states of a logical device and checking the order of occurrence of them and detecting the state transition of the logical device to stop debugging. CONSTITUTION:A debugging processing signal 100 which a logical device 10 sends is inputted to a memory 2, and contents of the address are sent as an order number 101 and is sent as an order number 102 through an output register 3. Numbers 101 and 102 are inputted to a comparator 4 and are checked, and an FF 6 is set to send a detection signal 104 if they are in a preliminarily set order. Next, a comparator 5 compares the number 101 with a preliminarily set end number 103, and a coincidence signal 105 is outputted if they coincide with each other. An AND gate 7 sends a debugging stop signal 106 when signals 104 and 105 coincide with each other. Thus, debugging is stopped by detecting the state transition of the logical device to improve the efficiency.
JP62233130A 1987-09-16 1987-09-16 Debugging control circuit Pending JPS6474637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62233130A JPS6474637A (en) 1987-09-16 1987-09-16 Debugging control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62233130A JPS6474637A (en) 1987-09-16 1987-09-16 Debugging control circuit

Publications (1)

Publication Number Publication Date
JPS6474637A true JPS6474637A (en) 1989-03-20

Family

ID=16950213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62233130A Pending JPS6474637A (en) 1987-09-16 1987-09-16 Debugging control circuit

Country Status (1)

Country Link
JP (1) JPS6474637A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008152544A (en) * 2006-12-18 2008-07-03 Hitachi Ltd Control microcomputer verification device and in-vehicle control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008152544A (en) * 2006-12-18 2008-07-03 Hitachi Ltd Control microcomputer verification device and in-vehicle control device

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