JPS6474824A - Bipolar logic circuit - Google Patents

Bipolar logic circuit

Info

Publication number
JPS6474824A
JPS6474824A JP23353087A JP23353087A JPS6474824A JP S6474824 A JPS6474824 A JP S6474824A JP 23353087 A JP23353087 A JP 23353087A JP 23353087 A JP23353087 A JP 23353087A JP S6474824 A JPS6474824 A JP S6474824A
Authority
JP
Japan
Prior art keywords
output terminal
power source
output
base
sbd11
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23353087A
Other languages
Japanese (ja)
Inventor
Koji Kitora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23353087A priority Critical patent/JPS6474824A/en
Publication of JPS6474824A publication Critical patent/JPS6474824A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To prevent the delay of tPLH (output L H propagation time) by charging output load capacitance quickly even when a noise is applied on an output terminal, by providing a transistor whose emitter is connected to the output terminal and whose collector is connected to a low potential power source terminal, and connecting a variable power source to the base. CONSTITUTION:The base potential of the transistor(TR)10 is set in the forward direction of an SBD11, and in case of applying the noise of negative voltage less than VF(SBD11)-VBE(Tr10) on the output terminal 4, the TR10 is energized, collector current with current amplification times the base current flows from a low potential power source 2. Since the current flows on the output terminal 4, the output load capacitance is charged quickly. As a result, a path from the emitter of the TR5 to the clamp SBD of the TR6 is interrupted, and the TR5 is set a de-energized state, thereby, the delay of the tPLH can be prevented from being generated.
JP23353087A 1987-09-16 1987-09-16 Bipolar logic circuit Pending JPS6474824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23353087A JPS6474824A (en) 1987-09-16 1987-09-16 Bipolar logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23353087A JPS6474824A (en) 1987-09-16 1987-09-16 Bipolar logic circuit

Publications (1)

Publication Number Publication Date
JPS6474824A true JPS6474824A (en) 1989-03-20

Family

ID=16956487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23353087A Pending JPS6474824A (en) 1987-09-16 1987-09-16 Bipolar logic circuit

Country Status (1)

Country Link
JP (1) JPS6474824A (en)

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