JPS6474872A - Picture processing circuit - Google Patents

Picture processing circuit

Info

Publication number
JPS6474872A
JPS6474872A JP62230956A JP23095687A JPS6474872A JP S6474872 A JPS6474872 A JP S6474872A JP 62230956 A JP62230956 A JP 62230956A JP 23095687 A JP23095687 A JP 23095687A JP S6474872 A JPS6474872 A JP S6474872A
Authority
JP
Japan
Prior art keywords
data
picture
outputted
output
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62230956A
Other languages
Japanese (ja)
Inventor
Kazuoki Hanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62230956A priority Critical patent/JPS6474872A/en
Publication of JPS6474872A publication Critical patent/JPS6474872A/en
Pending legal-status Critical Current

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  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To attain a simple picture processing with simple circuit constitution by handling the inverting output of a preceding picture element as picture- processed data. CONSTITUTION:An A/D converting circuit 1 converts the picture data, which are inputted from an external part, to a different threshold and sends it. Thus, for the output ot an OR gate 5 '1' is outputted when the respective thresholds are '1' and '0' is outputted when they are '0' respectively as the picture- processed data. When the data of the respective thresholds are gray areas, the inverse of Q output of a data delay circuit 6 is outputted through an AND gate 3 and the OR gate 5 as the picture-processed data. At such a time, the inverse of Q output is the inverting data of the preceding picture-processed data and for the data of the gray area, white and black are alternately outputted. Then, a half tone is artificially expressed.
JP62230956A 1987-09-17 1987-09-17 Picture processing circuit Pending JPS6474872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62230956A JPS6474872A (en) 1987-09-17 1987-09-17 Picture processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62230956A JPS6474872A (en) 1987-09-17 1987-09-17 Picture processing circuit

Publications (1)

Publication Number Publication Date
JPS6474872A true JPS6474872A (en) 1989-03-20

Family

ID=16915954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62230956A Pending JPS6474872A (en) 1987-09-17 1987-09-17 Picture processing circuit

Country Status (1)

Country Link
JP (1) JPS6474872A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444771U (en) * 1990-08-20 1992-04-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444771U (en) * 1990-08-20 1992-04-16

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