JPS6476092A - Image display device - Google Patents

Image display device

Info

Publication number
JPS6476092A
JPS6476092A JP62232226A JP23222687A JPS6476092A JP S6476092 A JPS6476092 A JP S6476092A JP 62232226 A JP62232226 A JP 62232226A JP 23222687 A JP23222687 A JP 23222687A JP S6476092 A JPS6476092 A JP S6476092A
Authority
JP
Japan
Prior art keywords
display
systems
crt
plotting speed
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62232226A
Other languages
Japanese (ja)
Inventor
Shigenori Watari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62232226A priority Critical patent/JPS6476092A/en
Publication of JPS6476092A publication Critical patent/JPS6476092A/en
Pending legal-status Critical Current

Links

Landscapes

  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To reduce memory capacity and to improve plotting speed by using a circuit constituted of a CRT controller, a frame memory and a shift register as two systems. CONSTITUTION: The circuit constituted of the CRT controller 1, the frame memory 2 and the shift register 3 is used as two systems. This device is provided with a circuit generating a multi-level signal expressing that the display is multi-level display when a scanning line exists at a window part, and uses an output bit number variable type output controller 4 changing the effective number of bits of display data output S3 and the kind of the data by using the multi-level signal and a priority system signal for deciding the order of priority of two systems. In the case the multi-level display and superimposed display are simultaneously executed on a CRT, a necessary storage quantity in substance becomes half and the number of bits per dot becomes half. Thus, the plotting speed becomes double, the memory capacity is reduced, and the plotting speed is improved.
JP62232226A 1987-09-18 1987-09-18 Image display device Pending JPS6476092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62232226A JPS6476092A (en) 1987-09-18 1987-09-18 Image display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62232226A JPS6476092A (en) 1987-09-18 1987-09-18 Image display device

Publications (1)

Publication Number Publication Date
JPS6476092A true JPS6476092A (en) 1989-03-22

Family

ID=16935954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62232226A Pending JPS6476092A (en) 1987-09-18 1987-09-18 Image display device

Country Status (1)

Country Link
JP (1) JPS6476092A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6636233B1 (en) 1999-02-18 2003-10-21 Nec Electronics Corporation Apparatus for processing two-dimensional images and method of doing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6636233B1 (en) 1999-02-18 2003-10-21 Nec Electronics Corporation Apparatus for processing two-dimensional images and method of doing the same

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