JPS6476146A - Bus coupling arbitrating system - Google Patents

Bus coupling arbitrating system

Info

Publication number
JPS6476146A
JPS6476146A JP23320187A JP23320187A JPS6476146A JP S6476146 A JPS6476146 A JP S6476146A JP 23320187 A JP23320187 A JP 23320187A JP 23320187 A JP23320187 A JP 23320187A JP S6476146 A JPS6476146 A JP S6476146A
Authority
JP
Japan
Prior art keywords
request
bus
bus cycle
priority
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23320187A
Other languages
Japanese (ja)
Inventor
Chitoshi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23320187A priority Critical patent/JPS6476146A/en
Publication of JPS6476146A publication Critical patent/JPS6476146A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To eliminate the load of a program by providing a priority at a mutual request when the request of the mutual use collides, executing the bus cycle error information to a requester having a lower priority and processing the request having a higher priority earlier. CONSTITUTION:A bus coupling arbitrating system CONAB1, when a request from a processor CPU1 and a CPU2 is received, acknowledges the request with the higher priority by the decision of the priority circuit of the internal part of the bus coupling arbitrating system CNAB 1, and executes a bus cycle error information to the request with the lower priority. The processor CPU 2 to receive the bus cycle error information stops the bus cycle by generating an error at the bus cycle execution, and a bus action is stopped until the bus cycle error is released. During the period, the bus cycle of the processor CPU1 with the higher priority operates a local memory MEM2 at the processor CPU2 side through a bus coupling part BUSCN1.
JP23320187A 1987-09-17 1987-09-17 Bus coupling arbitrating system Pending JPS6476146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23320187A JPS6476146A (en) 1987-09-17 1987-09-17 Bus coupling arbitrating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23320187A JPS6476146A (en) 1987-09-17 1987-09-17 Bus coupling arbitrating system

Publications (1)

Publication Number Publication Date
JPS6476146A true JPS6476146A (en) 1989-03-22

Family

ID=16951332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23320187A Pending JPS6476146A (en) 1987-09-17 1987-09-17 Bus coupling arbitrating system

Country Status (1)

Country Link
JP (1) JPS6476146A (en)

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