JPS6476342A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS6476342A
JPS6476342A JP23555987A JP23555987A JPS6476342A JP S6476342 A JPS6476342 A JP S6476342A JP 23555987 A JP23555987 A JP 23555987A JP 23555987 A JP23555987 A JP 23555987A JP S6476342 A JPS6476342 A JP S6476342A
Authority
JP
Japan
Prior art keywords
memory
memories
processor
processors
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23555987A
Other languages
Japanese (ja)
Inventor
Masami Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP23555987A priority Critical patent/JPS6476342A/en
Publication of JPS6476342A publication Critical patent/JPS6476342A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the efficiency of information processing by dividing memory data divided for each page into plural memories for storage and at the same time adding buses to plural processors respectively so that these processors can access those data stored in memories at one time. CONSTITUTION:When a memory access request is received from a processor l-i, for example, a control processor 3 identifies a specific memory 2-j that receives access from memories 2-1-2-m based on the access address of the processor l-i. In case the selected memory j-2 receives an access request also from another processor l-k, control is carried out to secure the connection to the memory 2-j in response to the priority orders set to those processors respectively. At the same time, the connection is performed so that unequivocal correspondence is secured to the memories requesting the buses of each processor in case these processors give the access requests to different memories respectively. In such constitution, plural processors can give memory accesses at a high speed.
JP23555987A 1987-09-18 1987-09-18 Information processing system Pending JPS6476342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23555987A JPS6476342A (en) 1987-09-18 1987-09-18 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23555987A JPS6476342A (en) 1987-09-18 1987-09-18 Information processing system

Publications (1)

Publication Number Publication Date
JPS6476342A true JPS6476342A (en) 1989-03-22

Family

ID=16987780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23555987A Pending JPS6476342A (en) 1987-09-18 1987-09-18 Information processing system

Country Status (1)

Country Link
JP (1) JPS6476342A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260107B1 (en) 1992-09-18 2001-07-10 Hitachi, Ltd Processor system using synchronous dynamic memory

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260107B1 (en) 1992-09-18 2001-07-10 Hitachi, Ltd Processor system using synchronous dynamic memory
US6697908B2 (en) 1992-09-18 2004-02-24 Renesas Technology Corporation Processor system using synchronous dynamic memory
US7143230B2 (en) 1992-09-18 2006-11-28 Renesas Technology Corp. Processor system using synchronous dynamic memory
US7376783B2 (en) 1992-09-18 2008-05-20 Renesas Technology Corp. Processor system using synchronous dynamic memory
US7904641B2 (en) 1992-09-18 2011-03-08 Renesas Technology Corporation Processor system using synchronous dynamic memory
US8234441B2 (en) 1992-09-18 2012-07-31 Renesas Electronics Corporation Processor system using synchronous dynamic memory

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