JPS6476593A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS6476593A
JPS6476593A JP23396087A JP23396087A JPS6476593A JP S6476593 A JPS6476593 A JP S6476593A JP 23396087 A JP23396087 A JP 23396087A JP 23396087 A JP23396087 A JP 23396087A JP S6476593 A JPS6476593 A JP S6476593A
Authority
JP
Japan
Prior art keywords
data lines
cdn
mosfets
feedback
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23396087A
Other languages
Japanese (ja)
Inventor
Hiroe Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23396087A priority Critical patent/JPS6476593A/en
Publication of JPS6476593A publication Critical patent/JPS6476593A/en
Pending legal-status Critical Current

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  • Read Only Memory (AREA)

Abstract

PURPOSE:To improve the reading margin of a micro-ROM and to prevent malfunction by providing first MOSFETs for feedback to further charge the electric potential of corresponding data lines and second MOSFETs to further discharge the levels of corresponding data lines. CONSTITUTION:The titled device is provided with inverter circuits N1 and N2 to receive the electric potentials of output lines of CD0-CDn, first MOSFETs Q3 and Q4 for feedback designed to have a comparatively small conductance and to charge the levels of the output lines CD0-CDn when the output signals of the inverter circuit N1-N2 are at a low level, and second MOSFET Q7 and Q8 for feedback to discharge the electric potentials of data lines D0-Dn when they are at high level. For this reason, the level lowering of the data lines D0-Dn and the output lines CD0-CDn by a leak, etc., is restrained and signal amplitude after a level decision becomes large. Thus, the reading margin of the micro-ROM is improved and its malfunction is prevented.
JP23396087A 1987-09-18 1987-09-18 Semiconductor memory device Pending JPS6476593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23396087A JPS6476593A (en) 1987-09-18 1987-09-18 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23396087A JPS6476593A (en) 1987-09-18 1987-09-18 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6476593A true JPS6476593A (en) 1989-03-22

Family

ID=16963325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23396087A Pending JPS6476593A (en) 1987-09-18 1987-09-18 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6476593A (en)

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