JPS6477150A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6477150A
JPS6477150A JP63183628A JP18362888A JPS6477150A JP S6477150 A JPS6477150 A JP S6477150A JP 63183628 A JP63183628 A JP 63183628A JP 18362888 A JP18362888 A JP 18362888A JP S6477150 A JPS6477150 A JP S6477150A
Authority
JP
Japan
Prior art keywords
electrodes
parts
base
ceramic base
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63183628A
Other languages
Japanese (ja)
Inventor
Kanji Otsuka
Masao Sekihashi
Takashi Araki
Masahiro Uesawa
Mutsuo Fuda
Satoshi Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP63183628A priority Critical patent/JPS6477150A/en
Publication of JPS6477150A publication Critical patent/JPS6477150A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make it possible to obtain fine electrodes and to realize the package of a high-integration semiconductor element by a method wherein the internal electrodes of the package are each constituted of each outer lead part formed by a printing technique and each inner lead part formed by deposition and so on. CONSTITUTION:A metallic layer 3 and internal electrodes 5 are formed by a method wherein a tungsten or molybdenum paste is first readyprinted at said places for the layer 3 and the electrodes 5 in the state of the green sheet of a ceramic base 1, then this is calcined and is metallized. The metallizing to the parts to correspond to the electrodes 5 is performed only to the parts to correspond to half of the outsides of the electrodes, which are formed radially, and these are used as outer lead parts 6. A semiconductor element 2 is bonded to the metallized layer 3 formed on the center of the base and element electrodes 4 and inner lead parts 13 of the electrodes 5 are connected to each other through wires 18. Moreover, a ceramic cap 19 is bonded on the upper surface of the base 1 with a bonding agent for protecting the element 2 and the element 2 is sealed. A heat dissipation body 20 and a heat dissipation fin are formed on the lower surface of the ceramic base integrally with the ceramic base.
JP63183628A 1988-07-25 1988-07-25 Manufacture of semiconductor device Pending JPS6477150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63183628A JPS6477150A (en) 1988-07-25 1988-07-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63183628A JPS6477150A (en) 1988-07-25 1988-07-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6477150A true JPS6477150A (en) 1989-03-23

Family

ID=16139097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63183628A Pending JPS6477150A (en) 1988-07-25 1988-07-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6477150A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531590A (en) * 1978-08-14 1980-03-05 Hilti Ag Drill hammer
JPS56129354A (en) * 1980-03-14 1981-10-09 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531590A (en) * 1978-08-14 1980-03-05 Hilti Ag Drill hammer
JPS56129354A (en) * 1980-03-14 1981-10-09 Hitachi Ltd Semiconductor device

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