JPS6477240A - Decoding device - Google Patents

Decoding device

Info

Publication number
JPS6477240A
JPS6477240A JP62232661A JP23266187A JPS6477240A JP S6477240 A JPS6477240 A JP S6477240A JP 62232661 A JP62232661 A JP 62232661A JP 23266187 A JP23266187 A JP 23266187A JP S6477240 A JPS6477240 A JP S6477240A
Authority
JP
Japan
Prior art keywords
error
decoding
data
timing
switching means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62232661A
Other languages
Japanese (ja)
Inventor
Hitoshi Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62232661A priority Critical patent/JPS6477240A/en
Publication of JPS6477240A publication Critical patent/JPS6477240A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To reduce data error due to step out by detecting a specific period when an error data counted value is minimum and settling the timing in accordance with the detection result. CONSTITUTION:The output signal of a second timing switching means 3 is decoded by a second decoding means 4, and its information pulse is given to an integral comparing circuit 6. This circuit 6 successively counts information pulses at the time of the change of designation of the phase or the like by a timing point changing means 5 and detects a minimum state of the counted value and outputs it to a first timing switching means 1. The first timing switching means 1 demodulates the phase in the least error state and divides data into blocks and outputs data to a first decoding means 2, and decoding like error correction is performed by the first decoding means 2. Since this decoding is performed in the least error state, obtained decoded data has the least error.
JP62232661A 1987-09-18 1987-09-18 Decoding device Pending JPS6477240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62232661A JPS6477240A (en) 1987-09-18 1987-09-18 Decoding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62232661A JPS6477240A (en) 1987-09-18 1987-09-18 Decoding device

Publications (1)

Publication Number Publication Date
JPS6477240A true JPS6477240A (en) 1989-03-23

Family

ID=16942809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62232661A Pending JPS6477240A (en) 1987-09-18 1987-09-18 Decoding device

Country Status (1)

Country Link
JP (1) JPS6477240A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160250867A1 (en) * 2015-02-26 2016-09-01 Canon Kabushiki Kaisha Recording method, recorded matter, recorded matter processing method, and method for improving fold-crack resistance of recorded matter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160250867A1 (en) * 2015-02-26 2016-09-01 Canon Kabushiki Kaisha Recording method, recorded matter, recorded matter processing method, and method for improving fold-crack resistance of recorded matter
US10384468B2 (en) * 2015-02-26 2019-08-20 Canon Kabushiki Kaisha Recording method, recorded matter, recorded matter processing method, and method for improving fold-crack resistance of recorded matter

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