JPS6478523A - Charge pump circuit for pll frequency synthesizer - Google Patents

Charge pump circuit for pll frequency synthesizer

Info

Publication number
JPS6478523A
JPS6478523A JP62235289A JP23528987A JPS6478523A JP S6478523 A JPS6478523 A JP S6478523A JP 62235289 A JP62235289 A JP 62235289A JP 23528987 A JP23528987 A JP 23528987A JP S6478523 A JPS6478523 A JP S6478523A
Authority
JP
Japan
Prior art keywords
pll
state
charge pump
pump circuit
lock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235289A
Other languages
Japanese (ja)
Inventor
Masaomi Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62235289A priority Critical patent/JPS6478523A/en
Publication of JPS6478523A publication Critical patent/JPS6478523A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To reduce noise after locking and to decrease the lockup time by selecting the quantity of the drive capability and outputting the result in detecting the unlock state or lock state of the PLL. CONSTITUTION:When a PLL lock detection circuit 26 detects the unlock state of the PLL, a changeover circuit 27 selects and outputs an output signal of large drive capability in 1st and 2nd pre-stage signal transmission circuits 22, 24 and 23, 25 and outputs an output signal with a small drive capability in detecting the lock state of the PLL. Thus, in case of the lock state, the gain constant of a phase detection circuit phi-DET 1 including the charge pump circuit 21 is small and the gain constant in the unlock state is large. Thus, the lockup time of the PLL is short in the unlock state and the noise of the PLL system is reduced in the lock state.
JP62235289A 1987-09-19 1987-09-19 Charge pump circuit for pll frequency synthesizer Pending JPS6478523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62235289A JPS6478523A (en) 1987-09-19 1987-09-19 Charge pump circuit for pll frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235289A JPS6478523A (en) 1987-09-19 1987-09-19 Charge pump circuit for pll frequency synthesizer

Publications (1)

Publication Number Publication Date
JPS6478523A true JPS6478523A (en) 1989-03-24

Family

ID=16983904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235289A Pending JPS6478523A (en) 1987-09-19 1987-09-19 Charge pump circuit for pll frequency synthesizer

Country Status (1)

Country Link
JP (1) JPS6478523A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429411A (en) * 1990-05-23 1992-01-31 Matsushita Electric Ind Co Ltd phase comparator
US5825570A (en) * 1994-03-18 1998-10-20 Fujitsu Limited PRML regenerating apparatus having reduced number of charge pump circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429411A (en) * 1990-05-23 1992-01-31 Matsushita Electric Ind Co Ltd phase comparator
US5825570A (en) * 1994-03-18 1998-10-20 Fujitsu Limited PRML regenerating apparatus having reduced number of charge pump circuits
US5841602A (en) * 1994-03-18 1998-11-24 Fujitsu Limited PRML regenerating apparatus
US5847891A (en) * 1994-03-18 1998-12-08 Fujitsu Limited PRML regenerating apparatus

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