JPS6479670A - Test circuit generation system - Google Patents

Test circuit generation system

Info

Publication number
JPS6479670A
JPS6479670A JP62236117A JP23611787A JPS6479670A JP S6479670 A JPS6479670 A JP S6479670A JP 62236117 A JP62236117 A JP 62236117A JP 23611787 A JP23611787 A JP 23611787A JP S6479670 A JPS6479670 A JP S6479670A
Authority
JP
Japan
Prior art keywords
circuit
test mode
selection line
tested
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62236117A
Other languages
Japanese (ja)
Inventor
Susumu Nitta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62236117A priority Critical patent/JPS6479670A/en
Publication of JPS6479670A publication Critical patent/JPS6479670A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To facilitate the testing without manual job, by automatically generating a multiplexer circuit and a demultiplexer circuit. CONSTITUTION:In a test mode, one of blocks 21 to be tested is selected with a test block selection line 24 and a signal from an external input line 22 is supplied with a test mode selection line 28 to the block being tested selected. In the test mode, an output of the block being tested as selected enters a multiplexer circuit 35 with a test mode selection line 32 passing through a demultiplexer circuit 31, selected with the selection line 24 and outputted to an external output line 36 to be observable outside. Thus, the output can be divided with a demultiplexer circuit 23, a multiplexer circuit 25, the circuit 31 and the circuit 35 to test thereby facilitating the testing without manual job.
JP62236117A 1987-09-22 1987-09-22 Test circuit generation system Pending JPS6479670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62236117A JPS6479670A (en) 1987-09-22 1987-09-22 Test circuit generation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62236117A JPS6479670A (en) 1987-09-22 1987-09-22 Test circuit generation system

Publications (1)

Publication Number Publication Date
JPS6479670A true JPS6479670A (en) 1989-03-24

Family

ID=16995992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62236117A Pending JPS6479670A (en) 1987-09-22 1987-09-22 Test circuit generation system

Country Status (1)

Country Link
JP (1) JPS6479670A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03128765U (en) * 1990-04-10 1991-12-25

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03128765U (en) * 1990-04-10 1991-12-25

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