JPS6479976A - 1-7 code converting circuit - Google Patents

1-7 code converting circuit

Info

Publication number
JPS6479976A
JPS6479976A JP23768887A JP23768887A JPS6479976A JP S6479976 A JPS6479976 A JP S6479976A JP 23768887 A JP23768887 A JP 23768887A JP 23768887 A JP23768887 A JP 23768887A JP S6479976 A JPS6479976 A JP S6479976A
Authority
JP
Japan
Prior art keywords
signal
circuit
code
bit
shifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23768887A
Other languages
Japanese (ja)
Other versions
JP2757360B2 (en
Inventor
Tetsuyuki Hishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23768887A priority Critical patent/JP2757360B2/en
Publication of JPS6479976A publication Critical patent/JPS6479976A/en
Application granted granted Critical
Publication of JP2757360B2 publication Critical patent/JP2757360B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To reduce the circuit quantity of a converting circuit by shifting decode data by 1 code.bit by means of a decoding circuit to 1-7-code-convert an analog signal which the head for writing and reading of a magnetic disk device reads. CONSTITUTION:A 1-7 code.bit signal 101 in which the analog signal read from the magnetic disk device is converted is inputted to a shift register circuit 1. By using a code.clock 102 of 1 data.clock, a signal 103 not shifted at all, a signal 104 shifted by 1 bit, and a signal 105 shifted by 2 bits are inputted to a gate circuit 2. The circuit 2 outputs a select 1-7 code.bit signal corresponding to strobe signals 110-112 sent from a decoding.control circuit 4 to a decoding circuit 3, and the circuit 4 executes a frame adjustment based on the information of converted NRZ signals 107 and 108. After the frame adjustment, a frame adjustment completion signal 113 is activated, and an NRZX1 signal 114 and an NRZX2 signal 115 can be transmitted to a high order device.
JP23768887A 1987-09-21 1987-09-21 1-7 code conversion circuit Expired - Lifetime JP2757360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23768887A JP2757360B2 (en) 1987-09-21 1987-09-21 1-7 code conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23768887A JP2757360B2 (en) 1987-09-21 1987-09-21 1-7 code conversion circuit

Publications (2)

Publication Number Publication Date
JPS6479976A true JPS6479976A (en) 1989-03-24
JP2757360B2 JP2757360B2 (en) 1998-05-25

Family

ID=17019035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23768887A Expired - Lifetime JP2757360B2 (en) 1987-09-21 1987-09-21 1-7 code conversion circuit

Country Status (1)

Country Link
JP (1) JP2757360B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007244370A (en) * 2006-02-14 2007-09-27 Yasuhiro Fujita Freely expandable sprawl wire for fishing, and device for fishing having the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007244370A (en) * 2006-02-14 2007-09-27 Yasuhiro Fujita Freely expandable sprawl wire for fishing, and device for fishing having the same

Also Published As

Publication number Publication date
JP2757360B2 (en) 1998-05-25

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