JPS6480062A - High withstand voltage unipolar and bipolar transistor - Google Patents
High withstand voltage unipolar and bipolar transistorInfo
- Publication number
- JPS6480062A JPS6480062A JP62238430A JP23843087A JPS6480062A JP S6480062 A JPS6480062 A JP S6480062A JP 62238430 A JP62238430 A JP 62238430A JP 23843087 A JP23843087 A JP 23843087A JP S6480062 A JPS6480062 A JP S6480062A
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- fet
- withstand voltage
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
- H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
- H10D84/406—Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
PURPOSE:To improve the apparent withstand voltage of a bipolar transistor by a method wherein the collector region of the bipolar transistor and the source region of a junction type FET are formed as a common region. CONSTITUTION:A base region 16a and an emitter region 17a are formed on the surface of the epitaxial layer 13 located on the left side of a collector region 15, and an n-p-n type transistor 1 is formed with said regions. The above- mentioned collector region 15 performs an additional function as the source region of an n-channel junction type FET. The above-mentioned FET 2 is composed of said source region 15, a gate region 20 and a drain region 17c. When the FET 2 is constituted as above and reverse voltage is applied to the n-p-n transistor 1, the FET 2 connected to the transistor 1 can be turned OFF. As a result, the apparent withstand voltage of the n-p-n transistor 1 can be enhanced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62238430A JPS6480062A (en) | 1987-09-21 | 1987-09-21 | High withstand voltage unipolar and bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62238430A JPS6480062A (en) | 1987-09-21 | 1987-09-21 | High withstand voltage unipolar and bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6480062A true JPS6480062A (en) | 1989-03-24 |
Family
ID=17030091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62238430A Pending JPS6480062A (en) | 1987-09-21 | 1987-09-21 | High withstand voltage unipolar and bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6480062A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017092474A (en) * | 2015-11-10 | 2017-05-25 | アナログ デバイシス グローバル | FET-bipolar transistor combination |
-
1987
- 1987-09-21 JP JP62238430A patent/JPS6480062A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017092474A (en) * | 2015-11-10 | 2017-05-25 | アナログ デバイシス グローバル | FET-bipolar transistor combination |
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