JPS6482131A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6482131A
JPS6482131A JP23935987A JP23935987A JPS6482131A JP S6482131 A JPS6482131 A JP S6482131A JP 23935987 A JP23935987 A JP 23935987A JP 23935987 A JP23935987 A JP 23935987A JP S6482131 A JPS6482131 A JP S6482131A
Authority
JP
Japan
Prior art keywords
instruction
instructions
data processor
detected
carry out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23935987A
Other languages
Japanese (ja)
Inventor
Yoshiki Shimoma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23935987A priority Critical patent/JPS6482131A/en
Publication of JPS6482131A publication Critical patent/JPS6482131A/en
Pending legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To carry out plural instructions in a single machine cycle by decoding simultaneously both an instruction and its subsequent instruction stored in an instruction buffer and processing these two instructions as a single proper instruction when a combination of specific instructions is detected. CONSTITUTION:An instruction buffer IB1 holds a pre-read instruction and an instruction decoder ID5 decodes the instruction held by the IB1. Then an instruction and its subsequent instruction stored in the IB1 are decoded at one time and then processed as a single proper instruction when a combination of specific instructions is detected. Thus it is possible to carry out plural instructions in a single machine cycle and to improve the performance of a data processor together with its high processing speed.
JP23935987A 1987-09-24 1987-09-24 Data processor Pending JPS6482131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23935987A JPS6482131A (en) 1987-09-24 1987-09-24 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23935987A JPS6482131A (en) 1987-09-24 1987-09-24 Data processor

Publications (1)

Publication Number Publication Date
JPS6482131A true JPS6482131A (en) 1989-03-28

Family

ID=17043584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23935987A Pending JPS6482131A (en) 1987-09-24 1987-09-24 Data processor

Country Status (1)

Country Link
JP (1) JPS6482131A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001016717A1 (en) * 1999-08-30 2001-03-08 Ip Flex Inc. Control unit and recorded medium
JP2004272927A (en) * 2004-04-26 2004-09-30 Matsushita Electric Ind Co Ltd Processor and compiling device
JP2005353105A (en) * 1999-04-30 2005-12-22 Renesas Technology Corp Data processing device and microcomputer
US7076638B2 (en) 2001-09-20 2006-07-11 Matsushita Electric Industrial Co., Ltd. Processor, compiler and compilation method
JP2006313561A (en) * 1999-04-30 2006-11-16 Renesas Technology Corp Data processor
JP2007310546A (en) * 2006-05-17 2007-11-29 Nec Computertechno Ltd Emulation method and computer system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818754A (en) * 1981-07-27 1983-02-03 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Instruction processing unit
JPS60176144A (en) * 1984-02-23 1985-09-10 Fujitsu Ltd Register file device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818754A (en) * 1981-07-27 1983-02-03 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Instruction processing unit
JPS60176144A (en) * 1984-02-23 1985-09-10 Fujitsu Ltd Register file device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353105A (en) * 1999-04-30 2005-12-22 Renesas Technology Corp Data processing device and microcomputer
JP2006313561A (en) * 1999-04-30 2006-11-16 Renesas Technology Corp Data processor
WO2001016717A1 (en) * 1999-08-30 2001-03-08 Ip Flex Inc. Control unit and recorded medium
US7076638B2 (en) 2001-09-20 2006-07-11 Matsushita Electric Industrial Co., Ltd. Processor, compiler and compilation method
US7761692B2 (en) 2001-09-20 2010-07-20 Panasonic Corporation Processor, compiler and compilation method
JP2004272927A (en) * 2004-04-26 2004-09-30 Matsushita Electric Ind Co Ltd Processor and compiling device
JP2007310546A (en) * 2006-05-17 2007-11-29 Nec Computertechno Ltd Emulation method and computer system
US8392893B2 (en) 2006-05-17 2013-03-05 Nec Computertechno, Ltd. Emulation method and computer system

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