JPS6482241A - Memory resetting circuit - Google Patents

Memory resetting circuit

Info

Publication number
JPS6482241A
JPS6482241A JP62238991A JP23899187A JPS6482241A JP S6482241 A JPS6482241 A JP S6482241A JP 62238991 A JP62238991 A JP 62238991A JP 23899187 A JP23899187 A JP 23899187A JP S6482241 A JPS6482241 A JP S6482241A
Authority
JP
Japan
Prior art keywords
circuit
parity
data
computed
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62238991A
Other languages
Japanese (ja)
Inventor
Fujio Cho
Toru Shibuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Miyagi Ltd
Original Assignee
NEC Corp
NEC Miyagi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Miyagi Ltd filed Critical NEC Corp
Priority to JP62238991A priority Critical patent/JPS6482241A/en
Publication of JPS6482241A publication Critical patent/JPS6482241A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To prevent continuation of erroneous data by resetting a memory circuit at the time of disaccord between the parity computed with data before input to the memory circuit and that computed with data of the output of the memory circuit. CONSTITUTION:With respect to data inputted from an input terminal 1, the parity is computed at intervals of a certain time by a parity computing circuit 2. This parity is inserted to input data by a multiplexing circuit 3 and is written in a memory circuit 4. The parity is detected from data read out from the circuit 4. A parity computing circuit 6 computes the parity by data read from the circuit 4 in the same cycle as parity computation in the circuit 2. It is discriminated by a discriminating circuit 7 whether the parity before input to the circuit 4 which is detected by the circuit 5 and the parity computed by the circuit 6 coincide with each other or not, and the circuit 4 is reset if they do not coincide with each other. Thus, continuation of erroneous data is prevented.
JP62238991A 1987-09-25 1987-09-25 Memory resetting circuit Pending JPS6482241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62238991A JPS6482241A (en) 1987-09-25 1987-09-25 Memory resetting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238991A JPS6482241A (en) 1987-09-25 1987-09-25 Memory resetting circuit

Publications (1)

Publication Number Publication Date
JPS6482241A true JPS6482241A (en) 1989-03-28

Family

ID=17038291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238991A Pending JPS6482241A (en) 1987-09-25 1987-09-25 Memory resetting circuit

Country Status (1)

Country Link
JP (1) JPS6482241A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137198A (en) * 1982-02-08 1983-08-15 Fujitsu Ltd Bit error detecting system of frame memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137198A (en) * 1982-02-08 1983-08-15 Fujitsu Ltd Bit error detecting system of frame memory

Similar Documents

Publication Publication Date Title
ES8701395A1 (en) ERROR DETECTION AND CORRECTION SYSTEM OF A DATA PROCESSING MEMORY UNIT.
CS321886A2 (en) Selfconfigurating storage circuit with selection by means of central processor
JPS6482241A (en) Memory resetting circuit
JPS6450148A (en) Memory resetting circuit
JPS5781644A (en) Coincidence detecting circuit
JPS56137450A (en) Runaway detection and returning device of operation processor
JPS6462736A (en) Error detecting circuit
JPS55105719A (en) Buffer device
JPS56140598A (en) Error control system of memory device
Ratcliff Caloric and/or Carbohydrate Calculator
JPS57188158A (en) Parity bit addition circuit
JPS57202153A (en) Pattern detecting circuit
JPS57188157A (en) Parity bit check circuit
JPS56132645A (en) Check system of input data selection signal for register
JPS57212576A (en) Demodulated data check system
JPS56137453A (en) Transfer system of error correction information
JPS5619596A (en) Parity error processing system
JPS577581A (en) Time generating device
JPS5733849A (en) Cyclic information transmission device
JPS6488649A (en) Microcomputer system
JPS56153592A (en) Output memory device
JPS5617442A (en) Parity error processing system
JPS56145600A (en) Detection system for memory destruction
JPS5621250A (en) Instruction retrial system
JPS5353932A (en) Fault detection system for memory address line